dmaengine: imx-sdma: Add multi fifo support

The i.MX SDMA engine can read from / write to multiple successive
hardware FIFO registers, referred to as "Multi FIFO support". This is
needed for the micfil driver and certain configurations of the SAI
driver. This patch adds support for this feature.

The number of FIFOs to read from / write to must be communicated from
the client driver to the SDMA engine. For this the struct
dma_slave_config::peripheral_config field is used.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-By: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220414162249.3934543-12-s.hauer@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 0e70843567cef7ee1735ba211d83238b99ee4354..95367a8a81a514ea943aaacd13fb4a7b52045e05 100644 (file)
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -14,6 +14,7 @@
 #include <linux/iopoll.h>
 #include <linux/module.h>
 #include <linux/types.h>
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/mm.h>
 #include <linux/interrupt.h>
@@ -73,6 +74,7 @@
 #define SDMA_CHNENBL0_IMX35    0x200
 #define SDMA_CHNENBL0_IMX31    0x080
 #define SDMA_CHNPRI_0          0x100
+#define SDMA_DONE0_CONFIG      0x1000
 
 /*
  * Buffer descriptor status values.
@@ -180,6 +182,12 @@
                                 BIT(DMA_MEM_TO_DEV) | \
                                 BIT(DMA_DEV_TO_DEV))
 
+#define SDMA_WATERMARK_LEVEL_N_FIFOS   GENMASK(15, 12)
+#define SDMA_WATERMARK_LEVEL_SW_DONE   BIT(23)
+
+#define SDMA_DONE0_CONFIG_DONE_SEL     BIT(7)
+#define SDMA_DONE0_CONFIG_DONE_DIS     BIT(6)
+
 /**
  * struct sdma_script_start_addrs - SDMA script start pointers
  *
@@ -441,6 +449,9 @@ struct sdma_channel {
        struct work_struct              terminate_worker;
        struct list_head                terminated;
        bool                            is_ram_script;
+       unsigned int                    n_fifos_src;
+       unsigned int                    n_fifos_dst;
+       bool                            sw_done;
 };
 
 #define IMX_DMA_SG_LOOP                BIT(0)
@@ -778,6 +789,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
        val = readl_relaxed(sdma->regs + chnenbl);
        __set_bit(channel, &val);
        writel_relaxed(val, sdma->regs + chnenbl);
+
+       /* Set SDMA_DONEx_CONFIG is sw_done enabled */
+       if (sdmac->sw_done) {
+               val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
+               val |= SDMA_DONE0_CONFIG_DONE_SEL;
+               val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
+               writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
+       }
 }
 
 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
@@ -1038,6 +1057,10 @@ static int sdma_get_pc(struct sdma_channel *sdmac,
        case IMX_DMATYPE_IPU_MEMORY:
                emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
                break;
+       case IMX_DMATYPE_MULTI_SAI:
+               per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
+               emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
+               break;
        default:
                dev_err(sdma->dev, "Unsupported transfer type %d\n",
                        peripheral_type);
@@ -1214,6 +1237,22 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
        sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
 }
 
+static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
+{
+       unsigned int n_fifos;
+
+       if (sdmac->sw_done)
+               sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
+
+       if (sdmac->direction == DMA_DEV_TO_MEM)
+               n_fifos = sdmac->n_fifos_src;
+       else
+               n_fifos = sdmac->n_fifos_dst;
+
+       sdmac->watermark_level |=
+                       FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos);
+}
+
 static int sdma_config_channel(struct dma_chan *chan)
 {
        struct sdma_channel *sdmac = to_sdma_chan(chan);
@@ -1250,6 +1289,10 @@ static int sdma_config_channel(struct dma_chan *chan)
                            sdmac->peripheral_type == IMX_DMATYPE_ASRC)
                                sdma_set_watermarklevel_for_p2p(sdmac);
                } else {
+                       if (sdmac->peripheral_type ==
+                                       IMX_DMATYPE_MULTI_SAI)
+                               sdma_set_watermarklevel_for_sais(sdmac);
+
                        __set_bit(sdmac->event_id0, sdmac->event_mask);
                }
 
@@ -1707,9 +1750,23 @@ static int sdma_config(struct dma_chan *chan,
                       struct dma_slave_config *dmaengine_cfg)
 {
        struct sdma_channel *sdmac = to_sdma_chan(chan);
+       struct sdma_engine *sdma = sdmac->sdma;
 
        memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
 
+       if (dmaengine_cfg->peripheral_config) {
+               struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
+               if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
+                       dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
+                               dmaengine_cfg->peripheral_size,
+                               sizeof(struct sdma_peripheral_config));
+                       return -EINVAL;
+               }
+               sdmac->n_fifos_src = sdmacfg->n_fifos_src;
+               sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
+               sdmac->sw_done = sdmacfg->sw_done;
+       }
+
        /* Set ENBLn earlier to make sure dma request triggered after that */
        if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
                return -EINVAL;

diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h
index b06cba85a6d46ee323b1581912c2fdf2f9bfec14..8887762360d40c8d3a03da9e4f4e72c07124cbc4 100644 (file)
--- a/include/linux/dma/imx-dma.h
+++ b/include/linux/dma/imx-dma.h
@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
        IMX_DMATYPE_SSI_DUAL,   /* SSI Dual FIFO */
        IMX_DMATYPE_ASRC_SP,    /* Shared ASRC */
        IMX_DMATYPE_SAI,        /* SAI */
+       IMX_DMATYPE_MULTI_SAI,  /* MULTI FIFOs For Audio */
 };
 
 enum imx_dma_prio {
@@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
                !strcmp(chan->device->dev->driver->name, "imx-dma");
 }
 
+/**
+ * struct sdma_peripheral_config - SDMA config for audio
+ * @n_fifos_src: Number of FIFOs for recording
+ * @n_fifos_dst: Number of FIFOs for playback
+ * @sw_done: Use software done. Needed for PDM (micfil)
+ *
+ * Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
+ * registers. For multichannel recording/playback the SAI/micfil have
+ * one FIFO register per channel and the SDMA engine has to read/write
+ * the next channel from/to the next register and wrap around to the
+ * first register when all channels are handled. The number of active
+ * channels must be communicated to the SDMA engine using this struct.
+ */
+struct sdma_peripheral_config {
+       int n_fifos_src;
+       int n_fifos_dst;
+       bool sw_done;
+};
+
 #endif /* __LINUX_DMA_IMX_H */