drm/amd/display: enable pipe power gating by default
authorSung Joon Kim <sungjoon.kim@amd.com>
Fri, 13 Nov 2020 16:01:19 +0000 (11:01 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 24 Nov 2020 17:08:42 +0000 (12:08 -0500)
[why]
ASIC requirement.

[how]
Make disable_*_power_gate to false.

Signed-off-by: Sung Joon Kim <sungjoon.kim@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

index 5f97808bb423d459b7ae7192d6ac4067326f015a..4b029631a22c26a7d38bda79006a065018692702 100644 (file)
@@ -850,8 +850,8 @@ static const struct dc_debug_options debug_defaults_drv = {
        .force_abm_enable = false,
        .timing_trace = false,
        .clock_trace = true,
-       .disable_dpp_power_gate = true,
-       .disable_hubp_power_gate = true,
+       .disable_dpp_power_gate = false,
+       .disable_hubp_power_gate = false,
        .disable_clock_gate = true,
        .disable_pplib_clock_request = true,
        .disable_pplib_wm_range = true,
@@ -873,8 +873,8 @@ static const struct dc_debug_options debug_defaults_diags = {
        .force_abm_enable = false,
        .timing_trace = true,
        .clock_trace = true,
-       .disable_dpp_power_gate = true,
-       .disable_hubp_power_gate = true,
+       .disable_dpp_power_gate = false,
+       .disable_hubp_power_gate = false,
        .disable_clock_gate = true,
        .disable_pplib_clock_request = true,
        .disable_pplib_wm_range = true,