Support rv32 ULEB128 test

Use opcodes available to both rv32 and rv64 in uleb128 module linking
test.

Fixes: af71bc194916 ("riscv: Add tests for riscv module loading")
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Closes: https://lore.kernel.org/lkml/1d7c71ee-5742-4df4-b8ef-a2aea0a624eb@infradead.org/
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Link: https://lore.kernel.org/r/20231122-module_fixup-v2-1-dfb9565e9ea5@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S
index 90f22049d553e0e99b73ccc1291a57a2fb48aa0e..8515ed7cd8c120f75d592c401aa383da629c5729 100644 (file)
--- a/arch/riscv/kernel/tests/module_test/test_uleb128.S
+++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S
@@ -6,13 +6,13 @@
 .text
 .global test_uleb_basic
 test_uleb_basic:
-       ld      a0, second
+       lw      a0, second
        addi    a0, a0, -127
        ret
 
 .global test_uleb_large
 test_uleb_large:
-       ld      a0, fourth
+       lw      a0, fourth
        addi    a0, a0, -0x07e8
        ret
 
@@ -22,10 +22,10 @@ first:
 second:
        .reloc second, R_RISCV_SET_ULEB128, second
        .reloc second, R_RISCV_SUB_ULEB128, first
-       .dword 0
+       .word 0
 third:
        .space 1000
 fourth:
        .reloc fourth, R_RISCV_SET_ULEB128, fourth
        .reloc fourth, R_RISCV_SUB_ULEB128, third
-       .dword 0
+       .word 0