drm/xe: Convert xe_mmio_wait32 to us so we can stop using wait_for_us.

Another clean-up towards killing the usage of i915_utils.h

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index b87bf3b4cd52d70d306739c6265f266bc9ab547c..1f7b68f61ec5e33f0770ebf780f21433e3c92388 100644 (file)
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -124,7 +124,8 @@ static int domain_wake_wait(struct xe_gt *gt,
                            struct xe_force_wake_domain *domain)
 {
        return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
-                             XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
+                             XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
+                             NULL);
 }
 
 static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -136,7 +137,8 @@ static int domain_sleep_wait(struct xe_gt *gt,
                             struct xe_force_wake_domain *domain)
 {
        return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
-                             XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
+                             XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
+                             NULL);
 }
 
 #define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 6a84d2a1c7f34d6718782c47eada43491f0415de..bdc64219ed4c850fdc65f9aad714bbffdd876b31 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -599,7 +599,8 @@ int do_gt_reset(struct xe_gt *gt)
        int err;
 
        xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
-       err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5, NULL);
+       err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,
+                            NULL);
        if (err)
                drm_err(&xe->drm,
                        "GT reset failed to clear GEN11_GRDOM_FULL\n");

diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 8add5ec9a30772d737de76ad1fa8e142d405f7d2..f4bfff98d5f4c77997f983100bb2efe2fdc37447 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -11,13 +11,6 @@
 
 #include "gt/intel_gt_regs.h"
 
-#include <linux/delay.h>
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporar
- * including so we can use 'wait_for'.
- */
-#include "i915_utils.h"
-
 /**
  * DOC: GT Multicast/Replicated (MCR) Register Support
  *
@@ -383,7 +376,7 @@ static void mcr_lock(struct xe_gt *gt)
         * shares the same steering control register.
         */
        if (GRAPHICS_VERx100(xe) >= 1270)
-               ret = wait_for_us(xe_mmio_read32(gt, STEER_SEMAPHORE) == 0x1, 10);
+               ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL);
 
        drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
 }

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 6ecf493c26b5e7a29d3019961ba978cd4c3cb25d..2deb1f6544ea6633a091a96cef45428bf9d4c394 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -324,7 +324,8 @@ int xe_guc_reset(struct xe_guc *guc)
 
        xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
 
-       ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5, &gdrst);
+       ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,
+                            &gdrst);
        if (ret) {
                drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
                        gdrst);
@@ -422,7 +423,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
        ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
                             FIELD_PREP(GS_UKERNEL_MASK,
                                        XE_GUC_LOAD_STATUS_READY),
-                            GS_UKERNEL_MASK, 200, &status);
+                            GS_UKERNEL_MASK, 200000, &status);
 
        if (ret) {
                struct drm_device *drm = &xe->drm;
@@ -670,7 +671,7 @@ retry:
        ret = xe_mmio_wait32(gt, reply_reg,
                             FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
                                        GUC_HXG_ORIGIN_GUC),
-                            GUC_HXG_MSG_0_ORIGIN, 50, &reply);
+                            GUC_HXG_MSG_0_ORIGIN, 50000, &reply);
        if (ret) {
 timeout:
                drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
@@ -685,7 +686,7 @@ timeout:
                ret = xe_mmio_wait32(gt, reply_reg,
                                     FIELD_PREP(GUC_HXG_MSG_0_TYPE,
                                                GUC_HXG_TYPE_RESPONSE_SUCCESS),
-                                    GUC_HXG_MSG_0_TYPE, 1000, &header);
+                                    GUC_HXG_MSG_0_TYPE, 1000000, &header);
 
                if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
                             GUC_HXG_ORIGIN_GUC))

diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index c8c93bdf4760fcebed2fe750be2a25877cbf09bb..9cb15bb40a385eae931d690e466028beaa6dfe4b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc)
 
        ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
                             HUC_LOAD_SUCCESSFUL,
-                            HUC_LOAD_SUCCESSFUL, 100, NULL);
+                            HUC_LOAD_SUCCESSFUL, 100000, NULL);
        if (ret) {
                drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);
                goto fail;

diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index ccd97a4a89c16160cc1d27048a61e22cbd671f71..f72edfb39cc019b1a3a8f09dfb76f49b02b2c5de 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -83,10 +83,10 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
 }
 
 static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
-                                u32 mask, u32 timeout_ms, u32 *out_val)
+                                u32 mask, u32 timeout_us, u32 *out_val)
 {
        ktime_t cur = ktime_get_raw();
-       const ktime_t end = ktime_add_ms(cur, timeout_ms);
+       const ktime_t end = ktime_add_us(cur, timeout_us);
        int ret = -ETIMEDOUT;
        s64 wait = 10;
        u32 read;

diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index edd6a5d2db34e91ba318e4cf37d446b357d049d7..bbb931bc19ce2e93dea09b0a1dc8ef888c07e008 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -352,7 +352,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
                        _MASKED_BIT_ENABLE(dma_flags | START_DMA));
 
        /* Wait for DMA to finish */
-       ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100, &dma_ctrl);
+       ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl);
        if (ret)
                drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
                        xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);