iommu/vt-d: Consolidate duplicate cache invaliation code

[ Upstream commit 9872f9bd9dbd68f75e8db782717d71e8594f6a02 ]

The pasid based IOTLB and devTLB invalidation code is duplicate in
several places. Consolidate them by using the common helpers.

Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210114085021.717041-1-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index 1e7c17989084e89e21d060af5244fffe08aa7bff..77fbe9908abdc39aca7af88ea502287a09463beb 100644 (file)
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -466,20 +466,6 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
        qi_submit_sync(iommu, &desc, 1, 0);
 }
 
-static void
-iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid)
-{
-       struct qi_desc desc;
-
-       desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) |
-                       QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
-       desc.qw1 = 0;
-       desc.qw2 = 0;
-       desc.qw3 = 0;
-
-       qi_submit_sync(iommu, &desc, 1, 0);
-}
-
 static void
 devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
                               struct device *dev, u32 pasid)
@@ -524,7 +510,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev,
                clflush_cache_range(pte, sizeof(*pte));
 
        pasid_cache_invalidation_with_pasid(iommu, did, pasid);
-       iotlb_invalidation_with_pasid(iommu, did, pasid);
+       qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
 
        /* Device IOTLB doesn't need to be flushed in caching mode. */
        if (!cap_caching_mode(iommu->cap))
@@ -540,7 +526,7 @@ static void pasid_flush_caches(struct intel_iommu *iommu,
 
        if (cap_caching_mode(iommu->cap)) {
                pasid_cache_invalidation_with_pasid(iommu, did, pasid);
-               iotlb_invalidation_with_pasid(iommu, did, pasid);
+               qi_flush_piotlb(iommu, did, pasid, 0, -1, 0);
        } else {
                iommu_flush_write_buffer(iommu);
        }

diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
index 6168dec7cb40d6f9955d0aaa8b80dd9671b49572..aabf56272b86d7da8fc0697e64a0e254f8886891 100644 (file)
--- a/drivers/iommu/intel/svm.c
+++ b/drivers/iommu/intel/svm.c
@@ -123,53 +123,16 @@ static void __flush_svm_range_dev(struct intel_svm *svm,
                                  unsigned long address,
                                  unsigned long pages, int ih)
 {
-       struct qi_desc desc;
+       struct device_domain_info *info = get_domain_info(sdev->dev);
 
-       if (pages == -1) {
-               desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
-                       QI_EIOTLB_DID(sdev->did) |
-                       QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
-                       QI_EIOTLB_TYPE;
-               desc.qw1 = 0;
-       } else {
-               int mask = ilog2(__roundup_pow_of_two(pages));
-
-               desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
-                               QI_EIOTLB_DID(sdev->did) |
-                               QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
-                               QI_EIOTLB_TYPE;
-               desc.qw1 = QI_EIOTLB_ADDR(address) |
-                               QI_EIOTLB_IH(ih) |
-                               QI_EIOTLB_AM(mask);
-       }
-       desc.qw2 = 0;
-       desc.qw3 = 0;
-       qi_submit_sync(sdev->iommu, &desc, 1, 0);
-
-       if (sdev->dev_iotlb) {
-               desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
-                               QI_DEV_EIOTLB_SID(sdev->sid) |
-                               QI_DEV_EIOTLB_QDEP(sdev->qdep) |
-                               QI_DEIOTLB_TYPE;
-               if (pages == -1) {
-                       desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
-                                       QI_DEV_EIOTLB_SIZE;
-               } else if (pages > 1) {
-                       /* The least significant zero bit indicates the size. So,
-                        * for example, an "address" value of 0x12345f000 will
-                        * flush from 0x123440000 to 0x12347ffff (256KiB). */
-                       unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
-                       unsigned long mask = __rounddown_pow_of_two(address ^ last);
-
-                       desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
-                                       (mask - 1)) | QI_DEV_EIOTLB_SIZE;
-               } else {
-                       desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
-               }
-               desc.qw2 = 0;
-               desc.qw3 = 0;
-               qi_submit_sync(sdev->iommu, &desc, 1, 0);
-       }
+       if (WARN_ON(!pages))
+               return;
+
+       qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, address, pages, ih);
+       if (info->ats_enabled)
+               qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info->pfsid,
+                                        svm->pasid, sdev->qdep, address,
+                                        order_base_2(pages));
 }
 
 static void intel_flush_svm_range_dev(struct intel_svm *svm,