return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val);
}
-#define FWDL_WAIT_CNT 400000
int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev)
{
u8 val;
static int rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len)
{
- u8 val;
int ret;
ret = __rtw89_fw_download_hdr(rtwdev, fw, len);
return ret;
}
- ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_FWDL_PATH_RDY,
- 1, FWDL_WAIT_CNT, false,
- rtwdev, R_AX_WCPU_FW_CTRL);
+ ret = rtw89_fwdl_check_path_ready_ax(rtwdev, false);
if (ret) {
rtw89_err(rtwdev, "[ERR]FWDL path ready\n");
return ret;
struct rtw89_fw_info *fw_info = &rtwdev->fw;
struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type);
struct rtw89_fw_bin_info info;
- u8 val;
int ret;
rtw89_mac_disable_cpu(rtwdev);
goto fwdl_err;
}
- ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_H2C_PATH_RDY,
- 1, FWDL_WAIT_CNT, false,
- rtwdev, R_AX_WCPU_FW_CTRL);
+ ret = rtw89_fwdl_check_path_ready_ax(rtwdev, true);
if (ret) {
rtw89_err(rtwdev, "[ERR]H2C path ready\n");
goto fwdl_err;
#define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
#define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
+#define FWDL_WAIT_CNT 400000
+
int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
return ret;
}
+int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev,
+ bool h2c_or_fwdl)
+{
+ u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY;
+ u8 val;
+
+ return read_poll_timeout_atomic(rtw89_read8, val, val & check,
+ 1, FWDL_WAIT_CNT, false,
+ rtwdev, R_AX_WCPU_FW_CTRL);
+}
+
const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
.band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET,
.filter_model_addr = R_AX_FILTER_MODEL_ADDR,