drm/amdgpu: add helper function to initialize mqd from ring v4
authorJack Xiao <Jack.Xiao@amd.com>
Wed, 1 Jul 2020 04:23:06 +0000 (12:23 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:03:14 +0000 (10:03 -0400)
Add the helper function to initialize mqd from ring configuration.

v2: use if/else pair instead of ?/: pair
v3: use simpler way to judge hqd_active
v4: fix parameters to amdgpu_gfx_is_high_priority_compute_queue

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

index 7f33ae87cb41e72b5edfe6d8d30f99bf3c6a4aa1..77395431821620313c6c5c40b8b6f077a60fe5c7 100644 (file)
@@ -458,3 +458,51 @@ int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
        ring->sched.ready = !r;
        return r;
 }
+
+static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring,
+                                   struct amdgpu_mqd_prop *prop)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       memset(prop, 0, sizeof(*prop));
+
+       prop->mqd_gpu_addr = ring->mqd_gpu_addr;
+       prop->hqd_base_gpu_addr = ring->gpu_addr;
+       prop->rptr_gpu_addr = ring->rptr_gpu_addr;
+       prop->wptr_gpu_addr = ring->wptr_gpu_addr;
+       prop->queue_size = ring->ring_size;
+       prop->eop_gpu_addr = ring->eop_gpu_addr;
+       prop->use_doorbell = ring->use_doorbell;
+       prop->doorbell_index = ring->doorbell_index;
+
+       /* map_queues packet doesn't need activate the queue,
+        * so only kiq need set this field.
+        */
+       prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ;
+
+       if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+               if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
+                       prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+                       prop->hqd_queue_priority =
+                               AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
+               }
+       }
+}
+
+int amdgpu_ring_init_mqd(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+       struct amdgpu_mqd *mqd_mgr;
+       struct amdgpu_mqd_prop prop;
+
+       amdgpu_ring_to_mqd_prop(ring, &prop);
+
+       ring->wptr = 0;
+
+       if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
+               mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE];
+       else
+               mqd_mgr = &adev->mqds[ring->funcs->type];
+
+       return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop);
+}
index 317d80209e9581bb7d3f767306959b6a199ba763..20dfe5a19a81f86f47081a18a941b131cac5847c 100644 (file)
@@ -369,6 +369,8 @@ int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
                              struct amdgpu_ring *ring);
 
+int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
+
 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
 {
        return ib->ptr[idx];