drivers/perf: hisi: Associate PMUs in SICL with CPUs online
authorQi Liu <liuqi115@huawei.com>
Fri, 15 Apr 2022 10:23:51 +0000 (18:23 +0800)
committerWill Deacon <will@kernel.org>
Fri, 6 May 2022 14:14:31 +0000 (15:14 +0100)
If a PMU is in a SICL (Super IO cluster), it is not appropriate to
associate this PMU with a CPU die. So we associate it with all CPUs
online, rather than CPUs in the nearest SCCL.

As the firmware of Hip09 platform hasn't been published yet, change
of PMU driver will not influence backwards compatibility between
driver and firmware.

Signed-off-by: Qi Liu <liuqi115@huawei.com>
Reviewed-by: John Garry <john.garry@huawei.com>
Link: https://lore.kernel.org/r/20220415102352.6665-2-liuqi115@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
drivers/perf/hisilicon/hisi_uncore_pmu.c
drivers/perf/hisilicon/hisi_uncore_pmu.h

index bad99d1491729af12f58e5b47beb581acaaa0d6b..a0ee84d97c41f99931db808a4bfcb658c538960f 100644 (file)
@@ -258,13 +258,12 @@ static int hisi_pa_pmu_init_data(struct platform_device *pdev,
                                   struct hisi_pmu *pa_pmu)
 {
        /*
-        * Use the SCCL_ID and the index ID to identify the PA PMU,
-        * while SCCL_ID is the nearst SCCL_ID from this SICL and
-        * CPU core is chosen from this SCCL to manage this PMU.
+        * As PA PMU is in a SICL, use the SICL_ID and the index ID
+        * to identify the PA PMU.
         */
        if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
-                                    &pa_pmu->sccl_id)) {
-               dev_err(&pdev->dev, "Cannot read sccl-id!\n");
+                                    &pa_pmu->sicl_id)) {
+               dev_err(&pdev->dev, "Cannot read sicl-id!\n");
                return -EINVAL;
        }
 
@@ -275,6 +274,7 @@ static int hisi_pa_pmu_init_data(struct platform_device *pdev,
        }
 
        pa_pmu->ccl_id = -1;
+       pa_pmu->sccl_id = -1;
 
        pa_pmu->base = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(pa_pmu->base)) {
@@ -399,13 +399,9 @@ static int hisi_pa_pmu_probe(struct platform_device *pdev)
        ret = hisi_pa_pmu_dev_probe(pdev, pa_pmu);
        if (ret)
                return ret;
-       /*
-        * PA is attached in SICL and the CPU core is chosen to manage this
-        * PMU which is the nearest SCCL, while its SCCL_ID is greater than
-        * one with the SICL_ID.
-        */
+
        name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sicl%u_pa%u",
-                             pa_pmu->sccl_id - 1, pa_pmu->index_id);
+                             pa_pmu->sicl_id, pa_pmu->index_id);
        if (!name)
                return -ENOMEM;
 
index 358e4e284a62905e64bfba49e58260005afb8761..980b9ee6eb149556d1fdee21171e47759346d2dc 100644 (file)
@@ -458,6 +458,10 @@ static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
 {
        int sccl_id, ccl_id;
 
+       /* If SCCL_ID is -1, the PMU is in a SICL and has no CPU affinity */
+       if (hisi_pmu->sccl_id == -1)
+               return true;
+
        if (hisi_pmu->ccl_id == -1) {
                /* If CCL_ID is -1, the PMU only shares the same SCCL */
                hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
index 7f5841d6f59246d72f08677466cf6096c8fa978a..96eeddad55ffce10a6e5781efa22d79816a78691 100644 (file)
@@ -81,6 +81,7 @@ struct hisi_pmu {
        struct device *dev;
        struct hlist_node node;
        int sccl_id;
+       int sicl_id;
        int ccl_id;
        void __iomem *base;
        /* the ID of the PMU modules */