drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk

Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.

v2: Adjust gvt accordingly

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240417151211.32135-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index d14e80ece8aaac91a396a025582bec31b3684d42..50d6b412d652463f74f189b00765ef3570e11e3e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -294,13 +294,13 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
        val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
        intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
 
-       val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
+       val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, 0));
        val &= ~(MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK);
        val |= MARGIN_000(trans->entries[level].bxt.margin) |
                UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale);
        intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
 
-       val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
+       val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0));
        val &= ~SCALE_DCOMP_METHOD;
        if (trans->entries[level].bxt.enable)
                val |= SCALE_DCOMP_METHOD;
@@ -311,7 +311,7 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
 
        intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
 
-       val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
+       val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, 0));
        val &= ~DE_EMPHASIS_MASK;
        val |= DE_EMPHASIS(trans->entries[level].bxt.deemphasis);
        intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4709b290be975dc8f3f13c6c7b59ff207dd50128..0258ae5185ade7f97fed458d41ddb79f28edd14a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2117,7 +2117,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
                drm_err(&i915->drm, "PLL %d not locked\n", port);
 
        if (IS_GEMINILAKE(i915)) {
-               temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch));
+               temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
                temp |= DCC_DELAY_RANGE_2;
                intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
        }

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index efcb00472be24779590fcce94753ab83a787f2c4..d36092615ae3990a1eeecddfafc2662649192c0d 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2763,15 +2763,15 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
 
        MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
                NULL, bxt_pcs_dw12_grp_write);
-       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
+       MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
                bxt_port_tx_dw3_read, NULL);
        MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
                NULL, bxt_pcs_dw12_grp_write);
-       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
+       MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
                bxt_port_tx_dw3_read, NULL);
        MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
                NULL, bxt_pcs_dw12_grp_write);
-       MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
+       MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
                bxt_port_tx_dw3_read, NULL);
        MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
        MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9701aad57e3ac689fa2bca7056178249c00629cb..261b520da3993bc825b94cb05c90793f48d0df67 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -555,6 +555,10 @@
                                         (reg_ch1) - _BXT_PHY0_BASE))
 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)            \
        _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
+#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 + \
+                                         ((lane) & 1) * 0x80)
+#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
+       _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
 
 #define BXT_P_CR_GT_DISP_PWRON         _MMIO(0x138090)
 #define  MIPIO_RST_CTRL                                (1 << 2)
@@ -747,18 +751,15 @@
                                                         _PORT_PCS_DW12_GRP_C)
 
 /* BXT PHY TX registers */
-#define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +      \
-                                         ((lane) & 1) * 0x80)
-
 #define _PORT_TX_DW2_LN0_A             0x162508
 #define _PORT_TX_DW2_LN0_B             0x6C508
 #define _PORT_TX_DW2_LN0_C             0x6C908
 #define _PORT_TX_DW2_GRP_A             0x162D08
 #define _PORT_TX_DW2_GRP_B             0x6CD08
 #define _PORT_TX_DW2_GRP_C             0x6CF08
-#define BXT_PORT_TX_DW2_LN0(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
-                                                        _PORT_TX_DW2_LN0_B, \
-                                                        _PORT_TX_DW2_LN0_C)
+#define BXT_PORT_TX_DW2_LN(phy, ch, lane)      _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
+                                                                   _PORT_TX_DW2_LN0_B, \
+                                                                   _PORT_TX_DW2_LN0_C)
 #define BXT_PORT_TX_DW2_GRP(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW2_GRP_B, \
                                                         _PORT_TX_DW2_GRP_C)
@@ -773,9 +774,9 @@
 #define _PORT_TX_DW3_GRP_A             0x162D0C
 #define _PORT_TX_DW3_GRP_B             0x6CD0C
 #define _PORT_TX_DW3_GRP_C             0x6CF0C
-#define BXT_PORT_TX_DW3_LN0(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
-                                                        _PORT_TX_DW3_LN0_B, \
-                                                        _PORT_TX_DW3_LN0_C)
+#define BXT_PORT_TX_DW3_LN(phy, ch, lane)      _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
+                                                                   _PORT_TX_DW3_LN0_B, \
+                                                                   _PORT_TX_DW3_LN0_C)
 #define BXT_PORT_TX_DW3_GRP(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW3_GRP_B, \
                                                         _PORT_TX_DW3_GRP_C)
@@ -788,9 +789,9 @@
 #define _PORT_TX_DW4_GRP_A             0x162D10
 #define _PORT_TX_DW4_GRP_B             0x6CD10
 #define _PORT_TX_DW4_GRP_C             0x6CF10
-#define BXT_PORT_TX_DW4_LN0(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
-                                                        _PORT_TX_DW4_LN0_B, \
-                                                        _PORT_TX_DW4_LN0_C)
+#define BXT_PORT_TX_DW4_LN(phy, ch, lane)      _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
+                                                                   _PORT_TX_DW4_LN0_B, \
+                                                                   _PORT_TX_DW4_LN0_C)
 #define BXT_PORT_TX_DW4_GRP(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW4_GRP_B, \
                                                         _PORT_TX_DW4_GRP_C)
@@ -803,9 +804,9 @@
 #define _PORT_TX_DW5_GRP_A             0x162D14
 #define _PORT_TX_DW5_GRP_B             0x6CD14
 #define _PORT_TX_DW5_GRP_C             0x6CF14
-#define BXT_PORT_TX_DW5_LN0(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
-                                                        _PORT_TX_DW5_LN0_B, \
-                                                        _PORT_TX_DW5_LN0_C)
+#define BXT_PORT_TX_DW5_LN(phy, ch, lane)      _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
+                                                                   _PORT_TX_DW5_LN0_B, \
+                                                                   _PORT_TX_DW5_LN0_C)
 #define BXT_PORT_TX_DW5_GRP(phy, ch)   _MMIO_BXT_PHY_CH(phy, ch, \
                                                         _PORT_TX_DW5_GRP_B, \
                                                         _PORT_TX_DW5_GRP_C)
@@ -816,10 +817,9 @@
 #define _PORT_TX_DW14_LN0_B            0x6C538
 #define _PORT_TX_DW14_LN0_C            0x6C938
 #define   LATENCY_OPTIM                        REG_BIT(30)
-#define BXT_PORT_TX_DW14_LN(phy, ch, lane)                             \
-       _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B,                 \
-                                  _PORT_TX_DW14_LN0_C) +               \
-             _BXT_LANE_OFFSET(lane))
+#define BXT_PORT_TX_DW14_LN(phy, ch, lane)     _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \
+                                                                   _PORT_TX_DW14_LN0_B, \
+                                                                   _PORT_TX_DW14_LN0_C)
 
 /* UAIMI scratch pad register 1 */
 #define UAIMI_SPR1                     _MMIO(0x4F074)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 87ecc5104fd9734ec02d9bebb80b435397544109..afb5b103df3e708da31dffe0506de24c0a5b22e9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1155,11 +1155,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0));
        MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0));
        MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1));
@@ -1180,11 +1180,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1));
        MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1));
        MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1));
-       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1));
+       MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY0, DPIO_CH1, 0));
        MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1));
-       MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1));
+       MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0));
        MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1));
-       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1));
+       MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY0, DPIO_CH1, 0));
        MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1));
@@ -1205,11 +1205,11 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0));
        MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0));
        MMIO_D(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW2_LN(DPIO_PHY1, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0));
-       MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0));
+       MMIO_D(BXT_PORT_TX_DW4_LN(DPIO_PHY1, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0));
        MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1));