Merge tag 'perf-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull perf fixes from Ingo Molnar:
 "Misc fixes, an expansion of perf syscall access to CAP_PERFMON
  privileged tools, plus a RAPL HW-enablement for Intel SPR platforms"

* tag 'perf-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/rapl: Add support for Intel SPR platform
  perf/x86/rapl: Support multiple RAPL unit quirks
  perf/x86/rapl: Fix missing psys sysfs attributes
  hw_breakpoint: Remove unused __register_perf_hw_breakpoint() declaration
  kprobes: Remove show_registers() function prototype
  perf/core: Take over CAP_SYS_PTRACE creds to CAP_PERFMON capability

diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 68b38820b10e8e869ad8050d72f4b8fc5a5dc9c1..67b411f7e8c41a6cea13376e1c358d355c85d179 100644 (file)
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -130,11 +130,17 @@ struct rapl_pmus {
        struct rapl_pmu         *pmus[];
 };
 
+enum rapl_unit_quirk {
+       RAPL_UNIT_QUIRK_NONE,
+       RAPL_UNIT_QUIRK_INTEL_HSW,
+       RAPL_UNIT_QUIRK_INTEL_SPR,
+};
+
 struct rapl_model {
        struct perf_msr *rapl_msrs;
        unsigned long   events;
        unsigned int    msr_power_unit;
-       bool            apply_quirk;
+       enum rapl_unit_quirk    unit_quirk;
 };
 
  /* 1/2^hw_unit Joule */
@@ -612,14 +618,28 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
        for (i = 0; i < NR_RAPL_DOMAINS; i++)
                rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
 
+       switch (rm->unit_quirk) {
        /*
         * DRAM domain on HSW server and KNL has fixed energy unit which can be
         * different than the unit from power unit MSR. See
         * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
         * of 2. Datasheet, September 2014, Reference Number: 330784-001 "
         */
-       if (rm->apply_quirk)
+       case RAPL_UNIT_QUIRK_INTEL_HSW:
+               rapl_hw_unit[PERF_RAPL_RAM] = 16;
+               break;
+       /*
+        * SPR shares the same DRAM domain energy unit as HSW, plus it
+        * also has a fixed energy unit for Psys domain.
+        */
+       case RAPL_UNIT_QUIRK_INTEL_SPR:
                rapl_hw_unit[PERF_RAPL_RAM] = 16;
+               rapl_hw_unit[PERF_RAPL_PSYS] = 0;
+               break;
+       default:
+               break;
+       }
+
 
        /*
         * Calculate the timer rate:
@@ -665,7 +685,7 @@ static const struct attribute_group *rapl_attr_update[] = {
        &rapl_events_pkg_group,
        &rapl_events_ram_group,
        &rapl_events_gpu_group,
-       &rapl_events_gpu_group,
+       &rapl_events_psys_group,
        NULL,
 };
 
@@ -698,7 +718,6 @@ static struct rapl_model model_snb = {
        .events         = BIT(PERF_RAPL_PP0) |
                          BIT(PERF_RAPL_PKG) |
                          BIT(PERF_RAPL_PP1),
-       .apply_quirk    = false,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
@@ -707,7 +726,6 @@ static struct rapl_model model_snbep = {
        .events         = BIT(PERF_RAPL_PP0) |
                          BIT(PERF_RAPL_PKG) |
                          BIT(PERF_RAPL_RAM),
-       .apply_quirk    = false,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
@@ -717,7 +735,6 @@ static struct rapl_model model_hsw = {
                          BIT(PERF_RAPL_PKG) |
                          BIT(PERF_RAPL_RAM) |
                          BIT(PERF_RAPL_PP1),
-       .apply_quirk    = false,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
@@ -726,7 +743,7 @@ static struct rapl_model model_hsx = {
        .events         = BIT(PERF_RAPL_PP0) |
                          BIT(PERF_RAPL_PKG) |
                          BIT(PERF_RAPL_RAM),
-       .apply_quirk    = true,
+       .unit_quirk     = RAPL_UNIT_QUIRK_INTEL_HSW,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
@@ -734,7 +751,7 @@ static struct rapl_model model_hsx = {
 static struct rapl_model model_knl = {
        .events         = BIT(PERF_RAPL_PKG) |
                          BIT(PERF_RAPL_RAM),
-       .apply_quirk    = true,
+       .unit_quirk     = RAPL_UNIT_QUIRK_INTEL_HSW,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
@@ -745,14 +762,22 @@ static struct rapl_model model_skl = {
                          BIT(PERF_RAPL_RAM) |
                          BIT(PERF_RAPL_PP1) |
                          BIT(PERF_RAPL_PSYS),
-       .apply_quirk    = false,
+       .msr_power_unit = MSR_RAPL_POWER_UNIT,
+       .rapl_msrs      = intel_rapl_msrs,
+};
+
+static struct rapl_model model_spr = {
+       .events         = BIT(PERF_RAPL_PP0) |
+                         BIT(PERF_RAPL_PKG) |
+                         BIT(PERF_RAPL_RAM) |
+                         BIT(PERF_RAPL_PSYS),
+       .unit_quirk     = RAPL_UNIT_QUIRK_INTEL_SPR,
        .msr_power_unit = MSR_RAPL_POWER_UNIT,
        .rapl_msrs      = intel_rapl_msrs,
 };
 
 static struct rapl_model model_amd_fam17h = {
        .events         = BIT(PERF_RAPL_PKG),
-       .apply_quirk    = false,
        .msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
        .rapl_msrs      = amd_rapl_msrs,
 };
@@ -787,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,           &model_hsx),
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,         &model_skl),
        X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,           &model_skl),
+       X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &model_spr),
        X86_MATCH_VENDOR_FAM(AMD,       0x17,           &model_amd_fam17h),
        X86_MATCH_VENDOR_FAM(HYGON,     0x18,           &model_amd_fam17h),
        {},

diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h
index d7d4250cd1e4490a22810deff8a9a13838df2164..78dd7035d1e542cac15edb3337951cce8e5d5e2d 100644 (file)
--- a/include/linux/hw_breakpoint.h
+++ b/include/linux/hw_breakpoint.h
@@ -72,7 +72,6 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr,
                            void *context);
 
 extern int register_perf_hw_breakpoint(struct perf_event *bp);
-extern int __register_perf_hw_breakpoint(struct perf_event *bp);
 extern void unregister_hw_breakpoint(struct perf_event *bp);
 extern void unregister_wide_hw_breakpoint(struct perf_event * __percpu *cpu_events);
 
@@ -119,8 +118,6 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr,
                            void *context)              { return NULL; }
 static inline int
 register_perf_hw_breakpoint(struct perf_event *bp)     { return -ENOSYS; }
-static inline int
-__register_perf_hw_breakpoint(struct perf_event *bp)   { return -ENOSYS; }
 static inline void unregister_hw_breakpoint(struct perf_event *bp)     { }
 static inline void
 unregister_wide_hw_breakpoint(struct perf_event * __percpu *cpu_events)        { }

diff --git a/kernel/events/core.c b/kernel/events/core.c
index 6961333ebad52bf63a9317c0338d234d50186192..5bfe8e3c6e443d8102abdbb67f39bcd6d2b4902e 100644 (file)
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -11706,7 +11706,7 @@ SYSCALL_DEFINE5(perf_event_open,
                        goto err_task;
 
                /*
-                * Reuse ptrace permission checks for now.
+                * Preserve ptrace permission check for backwards compatibility.
                 *
                 * We must hold exec_update_mutex across this and any potential
                 * perf_install_in_context() call for this new event to
@@ -11714,7 +11714,7 @@ SYSCALL_DEFINE5(perf_event_open,
                 * perf_event_exit_task() that could imply).
                 */
                err = -EACCES;
-               if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
+               if (!perfmon_capable() && !ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
                        goto err_cred;
        }