drm/sun4i: dotclock: Allow divider = 127

The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.

Make the end condition of the for loop inclusive of 127 in the
round_rate callback.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 1b6c2253192e43bef4accfc3b975e614dc2d4756..3eb99784f371bbc749c3fac8f6965f19773f38d4 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -77,7 +77,7 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
        u8 best_div = 1;
        int i;
 
-       for (i = 6; i < 127; i++) {
+       for (i = 6; i <= 127; i++) {
                unsigned long ideal = rate * i;
                unsigned long rounded;