Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk...

 - Various DT of_node refcount fixes
 - Support for fixed rate clks populated from an MMIO register
 - Remove clps711x driver as the board support is gone

* clk-of-refcount:
  clk: dove: fix refcount leak in dove_clk_init()
  clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init()
  clk: armada-xp: fix refcount leak in axp_clk_init()
  clk: kirkwood: fix refcount leak in kirkwood_clk_init()
  clk: armada-370: fix refcount leak in a370_clk_init()
  clk: vf610: fix refcount leak in vf610_clocks_init()
  clk: imx7d: fix refcount leak in imx7d_clocks_init()
  clk: imx6sx: fix refcount leak in imx6sx_clocks_init()
  clk: imx6q: fix refcount leak in imx6q_clocks_init()
  clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()
  clk: socfpga: fix refcount leak
  clk: ti: fix refcount leak in ti_dt_clocks_register()
  clk: qoriq: fix refcount leak in clockgen_init()
  clk: highbank: fix refcount leak in hb_clk_init()

* clk-mmio-fixed-clock:
  clk: Add Fixed MMIO clock driver
  dt-bindings: clk: Add bindings for Fixed MMIO clock

* clk-remove-clps:
  clk: clps711x: Remove board support

* clk-socfpga-parent:
  clk: socfpga: Don't have get_parent for single parent ops

* clk-struct-size:
  clk: imx: imx7ulp: use struct_size() in kzalloc()

diff --git a/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt
new file mode 100644 (file)
index 0000000..c359367
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt
@@ -0,0 +1,24 @@
+Binding for simple memory mapped io fixed-rate clock sources.
+The driver reads a clock frequency value from a single 32-bit memory mapped
+I/O register and registers it as a fixed rate clock.
+
+It was designed for test systems, like FPGA, not for complete, finished SoCs.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "fixed-mmio-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- reg : Address and length of the clock value register set.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+sysclock: sysclock@fd020004 {
+       #clock-cells = <0>;
+       compatible = "fixed-mmio-clock";
+       reg = <0xfd020004 0x4>;
+};

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index d2f0bb5ba47eabd3702a9c249f51f81f8d25a318..e705aab9e38ba8f6b82fc74ba74bbee5e3ec9843 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX
          This driver supports ROHM BD71837 and ROHM BD71847
          PMICs clock gates.
 
+config COMMON_CLK_FIXED_MMIO
+       bool "Clock driver for Memory Mapped Fixed values"
+       depends on COMMON_CLK && OF
+       help
+         Support for Memory Mapped IO Fixed clocks
+
 source "drivers/clk/actions/Kconfig"
 source "drivers/clk/bcm/Kconfig"
 source "drivers/clk/hisilicon/Kconfig"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8a9440a9750043ad80969367ed1938a6a9be1029..d6cd32bda771c15438a2fd06d031dab080461aa6 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925)      += clk-cdce925.o
 obj-$(CONFIG_ARCH_CLPS711X)            += clk-clps711x.o
 obj-$(CONFIG_COMMON_CLK_CS2000_CP)     += clk-cs2000-cp.o
 obj-$(CONFIG_ARCH_EFM32)               += clk-efm32gg.o
+obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)    += clk-fixed-mmio.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)                += clk-gemini.o
 obj-$(CONFIG_COMMON_CLK_ASPEED)                += clk-aspeed.o
 obj-$(CONFIG_ARCH_HIGHBANK)            += clk-highbank.o

diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c
index 2c04396402ab4a788f9d94c08db78bbcabd831ea..c36c47bdba0250fdf697e00aa845fb3abd9febd8 100644 (file)
--- a/drivers/clk/clk-clps711x.c
+++ b/drivers/clk/clk-clps711x.c
@@ -44,21 +44,21 @@ struct clps711x_clk {
        struct clk_hw_onecell_data      clk_data;
 };
 
-static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
-                                                      u32 fref)
+static void __init clps711x_clk_init_dt(struct device_node *np)
 {
-       u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;
+       u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
        struct clps711x_clk *clps711x_clk;
-       unsigned i;
+       void __iomem *base;
+
+       WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
 
-       if (!base)
-               return ERR_PTR(-ENOMEM);
+       base = of_iomap(np, 0);
+       BUG_ON(!base);
 
        clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
                                           CLPS711X_CLK_MAX),
                               GFP_KERNEL);
-       if (!clps711x_clk)
-               return ERR_PTR(-ENOMEM);
+       BUG_ON(!clps711x_clk);
 
        spin_lock_init(&clps711x_clk->lock);
 
@@ -137,52 +137,13 @@ static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
                clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
        clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
                clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
-       for (i = 0; i < CLPS711X_CLK_MAX; i++)
-               if (IS_ERR(clps711x_clk->clk_data.hws[i]))
+       for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
+               if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
                        pr_err("clk %i: register failed with %ld\n",
-                              i, PTR_ERR(clps711x_clk->clk_data.hws[i]));
-
-       return clps711x_clk;
-}
-
-void __init clps711x_clk_init(void __iomem *base)
-{
-       struct clps711x_clk *clps711x_clk;
-
-       clps711x_clk = _clps711x_clk_init(base, 73728000);
-
-       BUG_ON(IS_ERR(clps711x_clk));
-
-       /* Clocksource */
-       clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],
-                           NULL, "clps711x-timer.0");
-       clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],
-                           NULL, "clps711x-timer.1");
-
-       /* Drivers */
-       clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],
-                           NULL, "clps711x-pwm");
-       clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
-                           NULL, "clps711x-uart.0");
-       clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
-                           NULL, "clps711x-uart.1");
-}
-
-#ifdef CONFIG_OF
-static void __init clps711x_clk_init_dt(struct device_node *np)
-{
-       void __iomem *base = of_iomap(np, 0);
-       struct clps711x_clk *clps711x_clk;
-       u32 fref = 0;
-
-       WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
-
-       clps711x_clk = _clps711x_clk_init(base, fref);
-       BUG_ON(IS_ERR(clps711x_clk));
+                              tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
 
        clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
        of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
                               &clps711x_clk->clk_data);
 }
 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
-#endif

diff --git a/drivers/clk/clk-fixed-mmio.c b/drivers/clk/clk-fixed-mmio.c
new file mode 100644 (file)
index 0000000..d1a97d9
--- /dev/null
+++ b/drivers/clk/clk-fixed-mmio.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Memory Mapped IO Fixed clock driver
+ *
+ * Copyright (C) 2018 Cadence Design Systems, Inc.
+ *
+ * Authors:
+ *     Jan Kotas <jank@cadence.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)
+{
+       struct clk_hw *clk;
+       const char *clk_name = node->name;
+       void __iomem *base;
+       u32 freq;
+       int ret;
+
+       base = of_iomap(node, 0);
+       if (!base) {
+               pr_err("%pOFn: failed to map address\n", node);
+               return ERR_PTR(-EIO);
+       }
+
+       freq = readl(base);
+       iounmap(base);
+       of_property_read_string(node, "clock-output-names", &clk_name);
+
+       clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq);
+       if (IS_ERR(clk)) {
+               pr_err("%pOFn: failed to register fixed rate clock\n", node);
+               return clk;
+       }
+
+       ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk);
+       if (ret) {
+               pr_err("%pOFn: failed to add clock provider\n", node);
+               clk_hw_unregister(clk);
+               clk = ERR_PTR(ret);
+       }
+
+       return clk;
+}
+
+static void __init of_fixed_mmio_clk_setup(struct device_node *node)
+{
+       fixed_mmio_clk_setup(node);
+}
+CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
+
+/**
+ * This is not executed when of_fixed_mmio_clk_setup succeeded.
+ */
+static int of_fixed_mmio_clk_probe(struct platform_device *pdev)
+{
+       struct clk_hw *clk;
+
+       clk = fixed_mmio_clk_setup(pdev->dev.of_node);
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
+
+       platform_set_drvdata(pdev, clk);
+
+       return 0;
+}
+
+static int of_fixed_mmio_clk_remove(struct platform_device *pdev)
+{
+       struct clk_hw *clk = platform_get_drvdata(pdev);
+
+       of_clk_del_provider(pdev->dev.of_node);
+       clk_hw_unregister_fixed_rate(clk);
+
+       return 0;
+}
+
+static const struct of_device_id of_fixed_mmio_clk_ids[] = {
+       { .compatible = "fixed-mmio-clock" },
+       { }
+};
+MODULE_DEVICE_TABLE(of, of_fixed_mmio_clk_ids);
+
+static struct platform_driver of_fixed_mmio_clk_driver = {
+       .driver = {
+               .name = "of_fixed_mmio_clk",
+               .of_match_table = of_fixed_mmio_clk_ids,
+       },
+       .probe = of_fixed_mmio_clk_probe,
+       .remove = of_fixed_mmio_clk_remove,
+};
+module_platform_driver(of_fixed_mmio_clk_driver);
+
+MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
+MODULE_DESCRIPTION("Memory Mapped IO Fixed clock driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 727ed8e1bb726fd424f97427507abe6f46fe84a9..8e4581004695c44f11ea66250773c60720f4bbb8 100644 (file)
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -293,6 +293,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
        /* Map system registers */
        srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
        hb_clk->reg = of_iomap(srnp, 0);
+       of_node_put(srnp);
        BUG_ON(!hb_clk->reg);
        hb_clk->reg += reg;
 

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5baa9e051110c3036570b884b6914dd6245b0233..0e84f6dfa54e85eb664bb8ca395e9cb8afd15327 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -1389,6 +1389,7 @@ static void __init clockgen_init(struct device_node *np)
                                pr_err("%s: Couldn't map %pOF regs\n", __func__,
                                       guts);
                        }
+                       of_node_put(guts);
                }
 
        }

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 716eac3136b4d712f5865476db52188bf11b6a85..708e7c5590ddc89f01f691623748a731396fc26c 100644 (file)
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -471,6 +471,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
        anatop_base = base = of_iomap(np, 0);
        WARN_ON(!base);
+       of_node_put(np);
 
        /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
        if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {

diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index 18527a335ace30c1c8b308085578561b4f61f483..91558b09bf9eb04a92b60ab4a43a37e6ce4c19fa 100644 (file)
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -151,6 +151,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
        base = of_iomap(np, 0);
        WARN_ON(!base);
+       of_node_put(np);
 
        clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
        clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 06c105d580a45e75390e7ac87eb7b2641a6f5027..cfbd8d4edb8599b9cddbaec02f1a2832faa02bf7 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -404,6 +404,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
        base = of_iomap(np, 0);
        WARN_ON(!base);
+       of_node_put(np);
 
        clks[IMX7D_PLL_ARM_MAIN_SRC]  = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
        clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));

diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 4e18f629f8236284b6865c5dcd5ac3922ab72124..ce306631e84410d007afea1543a1c85df32fd0b7 100644 (file)
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -48,8 +48,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
        struct clk_hw **clks;
        void __iomem *base;
 
-       clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
-                          IMX7ULP_CLK_SCG1_END, GFP_KERNEL);
+       clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END),
+                          GFP_KERNEL);
        if (!clk_data)
                return;
 
@@ -136,8 +136,8 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
        struct clk_hw **clks;
        void __iomem *base;
 
-       clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
-                          IMX7ULP_CLK_PCC2_END, GFP_KERNEL);
+       clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
+                          GFP_KERNEL);
        if (!clk_data)
                return;
 
@@ -183,8 +183,8 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
        struct clk_hw **clks;
        void __iomem *base;
 
-       clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
-                          IMX7ULP_CLK_PCC3_END, GFP_KERNEL);
+       clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
+                          GFP_KERNEL);
        if (!clk_data)
                return;
 
@@ -228,8 +228,8 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np)
        struct clk_hw **clks;
        void __iomem *base;
 
-       clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *
-                          IMX7ULP_CLK_SMC1_END, GFP_KERNEL);
+       clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SMC1_END),
+                          GFP_KERNEL);
        if (!clk_data)
                return;
 

diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 6dae54325a91ddb32bb733b9d7d5cf48d0ecc023..a334667c450a1edf446e301e6be13b375a64053d 100644 (file)
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -203,6 +203,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
        np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
        anatop_base = of_iomap(np, 0);
        BUG_ON(!anatop_base);
+       of_node_put(np);
 
        np = ccm_node;
        ccm_base = of_iomap(np, 0);

diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
index 7dedfaa6e152033bd3f5e1e60dec8c28c86edfe9..5c6bbee396b3ce70a09dfb07a108cf2dc4a35c49 100644 (file)
--- a/drivers/clk/mvebu/armada-370.c
+++ b/drivers/clk/mvebu/armada-370.c
@@ -175,8 +175,10 @@ static void __init a370_clk_init(struct device_node *np)
 
        mvebu_coreclk_setup(np, &a370_coreclks);
 
-       if (cgnp)
+       if (cgnp) {
                mvebu_clk_gating_setup(cgnp, a370_gating_desc);
+               of_node_put(cgnp);
+       }
 }
 CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init);
 

diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index e8f03293ec833a97886269f21c648dff00f9d6fb..fa1568279c236c2db22a88e86cedce89c9c25dbf 100644 (file)
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -226,7 +226,9 @@ static void __init axp_clk_init(struct device_node *np)
 
        mvebu_coreclk_setup(np, &axp_coreclks);
 
-       if (cgnp)
+       if (cgnp) {
                mvebu_clk_gating_setup(cgnp, axp_gating_desc);
+               of_node_put(cgnp);
+       }
 }
 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);

diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
index e0dd99f36bf43dcdd8788e4e97c474a944daaa0b..0bd09d33f9cfeb3cd11851e2136542f4c46d709d 100644 (file)
--- a/drivers/clk/mvebu/dove.c
+++ b/drivers/clk/mvebu/dove.c
@@ -188,10 +188,14 @@ static void __init dove_clk_init(struct device_node *np)
 
        mvebu_coreclk_setup(np, &dove_coreclks);
 
-       if (ddnp)
+       if (ddnp) {
                dove_divider_clk_init(ddnp);
+               of_node_put(ddnp);
+       }
 
-       if (cgnp)
+       if (cgnp) {
                mvebu_clk_gating_setup(cgnp, dove_gating_desc);
+               of_node_put(cgnp);
+       }
 }
 CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);

diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
index 6f784167bda4a84c902b4f835070aa55cdd88b17..35af3aa18f1c44c7b929fd024c38c67d38c9acde 100644 (file)
--- a/drivers/clk/mvebu/kirkwood.c
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -331,6 +331,8 @@ static void __init kirkwood_clk_init(struct device_node *np)
        if (cgnp) {
                mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
                kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc);
+
+               of_node_put(cgnp);
        }
 }
 CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",

diff --git a/drivers/clk/mvebu/mv98dx3236.c b/drivers/clk/mvebu/mv98dx3236.c
index 0a74cf7a7725a01bcd647752c7d14656bc1c79ad..1c8ab4f834bab245def97ec47f49ea5d68c70155 100644 (file)
--- a/drivers/clk/mvebu/mv98dx3236.c
+++ b/drivers/clk/mvebu/mv98dx3236.c
@@ -172,7 +172,9 @@ static void __init mv98dx3236_clk_init(struct device_node *np)
 
        mvebu_coreclk_setup(np, &mv98dx3236_core_clocks);
 
-       if (cgnp)
+       if (cgnp) {
                mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+               of_node_put(cgnp);
+       }
 }
 CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init);

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 59d4d46667ce51d0043bb9d02e5f2d8b82179c93..54066e6508d3eeb259e89c82e1bf318d0379fa81 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1028,6 +1028,7 @@ static unsigned long __init exynos4_get_xom(void)
                        xom = readl(chipid_base + 8);
 
                iounmap(chipid_base);
+               of_node_put(np);
        }
 
        return xom;

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index aa7a6e6a15b656808d3cc9f92229125cb2baea81..73e03328d5c5af5eac1dffd8b7d51b054701b779 100644 (file)
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -176,8 +176,7 @@ static struct clk_ops gateclk_ops = {
        .set_parent = socfpga_clk_set_parent,
 };
 
-static void __init __socfpga_gate_init(struct device_node *node,
-       const struct clk_ops *ops)
+void __init socfpga_gate_init(struct device_node *node)
 {
        u32 clk_gate[2];
        u32 div_reg[3];
@@ -188,12 +187,17 @@ static void __init __socfpga_gate_init(struct device_node *node,
        const char *clk_name = node->name;
        const char *parent_name[SOCFPGA_MAX_PARENTS];
        struct clk_init_data init;
+       struct clk_ops *ops;
        int rc;
 
        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
        if (WARN_ON(!socfpga_clk))
                return;
 
+       ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
+       if (WARN_ON(!ops))
+               return;
+
        rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
        if (rc)
                clk_gate[0] = 0;
@@ -202,8 +206,8 @@ static void __init __socfpga_gate_init(struct device_node *node,
                socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
                socfpga_clk->hw.bit_idx = clk_gate[1];
 
-               gateclk_ops.enable = clk_gate_ops.enable;
-               gateclk_ops.disable = clk_gate_ops.disable;
+               ops->enable = clk_gate_ops.enable;
+               ops->disable = clk_gate_ops.disable;
        }
 
        rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
@@ -234,6 +238,11 @@ static void __init __socfpga_gate_init(struct device_node *node,
        init.flags = 0;
 
        init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
+       if (init.num_parents < 2) {
+               ops->get_parent = NULL;
+               ops->set_parent = NULL;
+       }
+
        init.parent_names = parent_name;
        socfpga_clk->hw.hw.init = &init;
 
@@ -246,8 +255,3 @@ static void __init __socfpga_gate_init(struct device_node *node,
        if (WARN_ON(rc))
                return;
 }
-
-void __init socfpga_gate_init(struct device_node *node)
-{
-       __socfpga_gate_init(node, &gateclk_ops);
-}

diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 35fabe1a32c30e4b400a77205c892f150b3f5f7c..269467e8e07e13a38399899c75194a347873c658 100644 (file)
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -95,6 +95,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
 
        clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
        clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
+       of_node_put(clkmgr_np);
        BUG_ON(!clk_mgr_a10_base_addr);
        pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
 

diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index c7f463172e4b93d0cec4b46e45558a301aa16234..b4b44e9b5901132a4849261d1563a6f3a797a469 100644 (file)
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -100,6 +100,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 
        clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
        clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
+       of_node_put(clkmgr_np);
        BUG_ON(!clk_mgr_base_addr);
        pll_clk->hw.reg = clk_mgr_base_addr + reg;
 

diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index d0cd58534781d8b51f62fc256f30d0d04d96182a..5174f9a916795dc0d42eef6bf6b287c6339a5d3a 100644 (file)
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -191,9 +191,13 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
                        clkdev_add(&c->lk);
                } else {
                        if (num_args && !has_clkctrl_data) {
-                               if (of_find_compatible_node(NULL, NULL,
-                                                           "ti,clkctrl")) {
+                               struct device_node *np;
+
+                               np = of_find_compatible_node(NULL, NULL,
+                                                            "ti,clkctrl");
+                               if (np) {
                                        has_clkctrl_data = true;
+                                       of_node_put(np);
                                } else {
                                        clkctrl_nodes_missing = true;