obj-y += io.o
obj-y += irq.o
-obj-y += flowctrl.o
obj-y += pm.o
obj-y += reset.o
obj-y += reset-handler.o
#include <linux/kernel.h>
#include <linux/module.h>
+#include <soc/tegra/flowctrl.h>
+
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "cpuidle.h"
-#include "flowctrl.h"
#include "iomap.h"
#include "irq.h"
#include "pm.h"
+++ /dev/null
-/*
- * arch/arm/mach-tegra/flowctrl.c
- *
- * functions and macros to control the flowcontroller
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/cpumask.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <soc/tegra/fuse.h>
-
-#include "flowctrl.h"
-
-static u8 flowctrl_offset_halt_cpu[] = {
- FLOW_CTRL_HALT_CPU0_EVENTS,
- FLOW_CTRL_HALT_CPU1_EVENTS,
- FLOW_CTRL_HALT_CPU1_EVENTS + 8,
- FLOW_CTRL_HALT_CPU1_EVENTS + 16,
-};
-
-static u8 flowctrl_offset_cpu_csr[] = {
- FLOW_CTRL_CPU0_CSR,
- FLOW_CTRL_CPU1_CSR,
- FLOW_CTRL_CPU1_CSR + 8,
- FLOW_CTRL_CPU1_CSR + 16,
-};
-
-static void __iomem *tegra_flowctrl_base;
-
-static void flowctrl_update(u8 offset, u32 value)
-{
- writel(value, tegra_flowctrl_base + offset);
-
- /* ensure the update has reached the flow controller */
- wmb();
- readl_relaxed(tegra_flowctrl_base + offset);
-}
-
-u32 flowctrl_read_cpu_csr(unsigned int cpuid)
-{
- u8 offset = flowctrl_offset_cpu_csr[cpuid];
-
- return readl(tegra_flowctrl_base + offset);
-}
-
-void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
-{
- return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
-}
-
-void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
-{
- return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
-}
-
-void flowctrl_cpu_suspend_enter(unsigned int cpuid)
-{
- unsigned int reg;
- int i;
-
- reg = flowctrl_read_cpu_csr(cpuid);
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- /* clear wfe bitmap */
- reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
- /* clear wfi bitmap */
- reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
- /* pwr gating on wfe */
- reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
- break;
- case TEGRA30:
- case TEGRA114:
- case TEGRA124:
- /* clear wfe bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
- /* clear wfi bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
- /* pwr gating on wfi */
- reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
- break;
- }
- reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
- reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
- reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
- flowctrl_write_cpu_csr(cpuid, reg);
-
- for (i = 0; i < num_possible_cpus(); i++) {
- if (i == cpuid)
- continue;
- reg = flowctrl_read_cpu_csr(i);
- reg |= FLOW_CTRL_CSR_EVENT_FLAG;
- reg |= FLOW_CTRL_CSR_INTR_FLAG;
- flowctrl_write_cpu_csr(i, reg);
- }
-}
-
-void flowctrl_cpu_suspend_exit(unsigned int cpuid)
-{
- unsigned int reg;
-
- /* Disable powergating via flow controller for CPU0 */
- reg = flowctrl_read_cpu_csr(cpuid);
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- /* clear wfe bitmap */
- reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
- /* clear wfi bitmap */
- reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
- break;
- case TEGRA30:
- case TEGRA114:
- case TEGRA124:
- /* clear wfe bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
- /* clear wfi bitmap */
- reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
- break;
- }
- reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
- reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
- reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
- flowctrl_write_cpu_csr(cpuid, reg);
-}
-
-static const struct of_device_id matches[] __initconst = {
- { .compatible = "nvidia,tegra124-flowctrl" },
- { .compatible = "nvidia,tegra114-flowctrl" },
- { .compatible = "nvidia,tegra30-flowctrl" },
- { .compatible = "nvidia,tegra20-flowctrl" },
- { }
-};
-
-void __init tegra_flowctrl_init(void)
-{
- /* hardcoded fallback if device tree node is missing */
- unsigned long base = 0x60007000;
- unsigned long size = SZ_4K;
- struct device_node *np;
-
- np = of_find_matching_node(NULL, matches);
- if (np) {
- struct resource res;
-
- if (of_address_to_resource(np, 0, &res) == 0) {
- size = resource_size(&res);
- base = res.start;
- }
-
- of_node_put(np);
- }
-
- tegra_flowctrl_base = ioremap_nocache(base, size);
-}
+++ /dev/null
-/*
- * arch/arm/mach-tegra/flowctrl.h
- *
- * functions and macros to control the flowcontroller
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __MACH_TEGRA_FLOWCTRL_H
-#define __MACH_TEGRA_FLOWCTRL_H
-
-#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
-#define FLOW_CTRL_WAITEVENT (2 << 29)
-#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
-#define FLOW_CTRL_JTAG_RESUME (1 << 28)
-#define FLOW_CTRL_SCLK_RESUME (1 << 27)
-#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
-#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
-#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
-#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
-#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
-#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
-#define FLOW_CTRL_CPU0_CSR 0x8
-#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
-#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
-#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
-#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
-#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
- FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
- FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
-#define FLOW_CTRL_CSR_ENABLE (1 << 0)
-#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
-#define FLOW_CTRL_CPU1_CSR 0x18
-
-#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
-#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
-#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
-
-#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
-#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
-#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
-
-#ifndef __ASSEMBLY__
-u32 flowctrl_read_cpu_csr(unsigned int cpuid);
-void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
-void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
-
-void flowctrl_cpu_suspend_enter(unsigned int cpuid);
-void flowctrl_cpu_suspend_exit(unsigned int cpuid);
-
-void tegra_flowctrl_init(void);
-#endif
-
-#endif
#include <linux/jiffies.h>
#include <linux/smp.h>
+#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h>
#include <asm/smp_scu.h>
#include "common.h"
-#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"
#include <linux/spinlock.h>
#include <linux/suspend.h>
+#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pm.h>
#include <soc/tegra/pmc.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
-#include "flowctrl.h"
#include "iomap.h"
#include "pm.h"
#include "reset.h"
#include <linux/init.h>
#include <linux/linkage.h>
+#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
-#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"
#include <linux/linkage.h>
+#include <soc/tegra/flowctrl.h>
+
#include <asm/assembler.h>
#include <asm/proc-fns.h>
#include <asm/cp15.h>
#include "irammap.h"
#include "sleep.h"
-#include "flowctrl.h"
#define EMC_CFG 0xc
#define EMC_ADR_CFG 0x10
#include <linux/linkage.h>
+#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
#include <asm/cache.h>
-#include "flowctrl.h"
#include "irammap.h"
#include "sleep.h"
#include "board.h"
#include "common.h"
#include "cpuidle.h"
-#include "flowctrl.h"
#include "iomap.h"
#include "irq.h"
#include "pm.h"
{
of_register_trusted_foundations();
tegra_cpu_reset_handler_init();
- tegra_flowctrl_init();
}
static void __init tegra_dt_init_irq(void)
select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
+ select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
select ARM_ERRATA_764369 if SMP
select PINCTRL_TEGRA30
select PL310_ERRATA_769419 if CACHE_L2X0
+ select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA114
+ select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
bool "Enable support for Tegra124 family"
select HAVE_ARM_ARCH_TIMER
select PINCTRL_TEGRA124
+ select SOC_TEGRA_FLOWCTRL
select SOC_TEGRA_PMC
select TEGRA_TIMER
help
endif
endif
+config SOC_TEGRA_FLOWCTRL
+ bool
+
config SOC_TEGRA_PMC
bool
obj-y += fuse/
obj-y += common.o
+obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o
--- /dev/null
+/*
+ * drivers/soc/tegra/flowctrl.c
+ *
+ * Functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/flowctrl.h>
+#include <soc/tegra/fuse.h>
+
+static u8 flowctrl_offset_halt_cpu[] = {
+ FLOW_CTRL_HALT_CPU0_EVENTS,
+ FLOW_CTRL_HALT_CPU1_EVENTS,
+ FLOW_CTRL_HALT_CPU1_EVENTS + 8,
+ FLOW_CTRL_HALT_CPU1_EVENTS + 16,
+};
+
+static u8 flowctrl_offset_cpu_csr[] = {
+ FLOW_CTRL_CPU0_CSR,
+ FLOW_CTRL_CPU1_CSR,
+ FLOW_CTRL_CPU1_CSR + 8,
+ FLOW_CTRL_CPU1_CSR + 16,
+};
+
+static void __iomem *tegra_flowctrl_base;
+
+static void flowctrl_update(u8 offset, u32 value)
+{
+ if (WARN_ONCE(!tegra_flowctrl_base,
+ "Tegra flowctrl not initialised!\n"))
+ return;
+
+ writel(value, tegra_flowctrl_base + offset);
+
+ /* ensure the update has reached the flow controller */
+ wmb();
+ readl_relaxed(tegra_flowctrl_base + offset);
+}
+
+u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+ u8 offset = flowctrl_offset_cpu_csr[cpuid];
+
+ if (WARN_ONCE(!tegra_flowctrl_base,
+ "Tegra flowctrl not initialised!\n"))
+ return 0;
+
+ return readl(tegra_flowctrl_base + offset);
+}
+
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
+{
+ return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
+}
+
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
+{
+ return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
+}
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+ unsigned int reg;
+ int i;
+
+ reg = flowctrl_read_cpu_csr(cpuid);
+ switch (tegra_get_chip_id()) {
+ case TEGRA20:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+ /* pwr gating on wfe */
+ reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
+ break;
+ case TEGRA30:
+ case TEGRA114:
+ case TEGRA124:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+ /* pwr gating on wfi */
+ reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
+ break;
+ }
+ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
+ reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
+ flowctrl_write_cpu_csr(cpuid, reg);
+
+ for (i = 0; i < num_possible_cpus(); i++) {
+ if (i == cpuid)
+ continue;
+ reg = flowctrl_read_cpu_csr(i);
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG;
+ reg |= FLOW_CTRL_CSR_INTR_FLAG;
+ flowctrl_write_cpu_csr(i, reg);
+ }
+}
+
+void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+ unsigned int reg;
+
+ /* Disable powergating via flow controller for CPU0 */
+ reg = flowctrl_read_cpu_csr(cpuid);
+ switch (tegra_get_chip_id()) {
+ case TEGRA20:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
+ break;
+ case TEGRA30:
+ case TEGRA114:
+ case TEGRA124:
+ /* clear wfe bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
+ /* clear wfi bitmap */
+ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
+ break;
+ }
+ reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
+ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
+ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
+ flowctrl_write_cpu_csr(cpuid, reg);
+}
+
+static const struct of_device_id matches[] __initconst = {
+ { .compatible = "nvidia,tegra124-flowctrl" },
+ { .compatible = "nvidia,tegra114-flowctrl" },
+ { .compatible = "nvidia,tegra30-flowctrl" },
+ { .compatible = "nvidia,tegra20-flowctrl" },
+ { }
+};
+
+static int __init tegra_flowctrl_init(void)
+{
+ /* hardcoded fallback if device tree node is missing */
+ unsigned long base = 0x60007000;
+ unsigned long size = SZ_4K;
+ struct device_node *np;
+
+ if (!soc_is_tegra())
+ return 0;
+
+ np = of_find_matching_node(NULL, matches);
+ if (np) {
+ struct resource res;
+
+ if (of_address_to_resource(np, 0, &res) == 0) {
+ size = resource_size(&res);
+ base = res.start;
+ }
+
+ of_node_put(np);
+ }
+
+ tegra_flowctrl_base = ioremap_nocache(base, size);
+ if (!tegra_flowctrl_base)
+ return -ENXIO;
+
+ return 0;
+}
+early_initcall(tegra_flowctrl_init);
--- /dev/null
+/*
+ * Functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_TEGRA_FLOWCTRL_H__
+#define __SOC_TEGRA_FLOWCTRL_H__
+
+#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
+#define FLOW_CTRL_WAITEVENT (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
+#define FLOW_CTRL_JTAG_RESUME (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME (1 << 27)
+#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
+#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
+#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
+#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
+#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
+#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
+#define FLOW_CTRL_CPU0_CSR 0x8
+#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
+#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
+#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
+ FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
+ FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
+#define FLOW_CTRL_CSR_ENABLE (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
+#define FLOW_CTRL_CPU1_CSR 0x18
+
+#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
+#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
+
+#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
+#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
+#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
+u32 flowctrl_read_cpu_csr(unsigned int cpuid);
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+
+void flowctrl_cpu_suspend_enter(unsigned int cpuid);
+void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+#else
+static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
+{
+ return 0;
+}
+
+static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
+{
+}
+
+static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
+
+static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
+{
+}
+
+static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
+{
+}
+#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
+#endif /* __ASSEMBLY */
+#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
projects / linux-2.6-block.git / commitdiff