drm/xe/xe2hpm: Add initial set of workarounds

Define the initial set of workarounds for Xe2_HPM.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-12-balasubramani.vivekanandan@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 0ce79ba19bda6178683cbefd5f658223b4ad0bfa..8fe811ea404a3de50a22379a9557e36ed1089a5c 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -280,6 +280,10 @@
 #define FORCEWAKE_GT                           XE_REG(0xa188)
 
 #define PG_ENABLE                              XE_REG(0xa210)
+#define   VD2_MFXVDENC_POWERGATE_ENABLE                REG_BIT(8)
+#define   VD2_HCP_POWERGATE_ENABLE             REG_BIT(7)
+#define   VD0_MFXVDENC_POWERGATE_ENABLE                REG_BIT(4)
+#define   VD0_HCP_POWERGATE_ENABLE             REG_BIT(3)
 
 #define CTC_MODE                               XE_REG(0xa26c)
 #define   CTC_SHIFT_PARAMETER_MASK             REG_GENMASK(2, 1)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 014d27c126ae90e84f11161ffd314fff77c34774..632bd9066f8da5f8ea9b91de3c27ab56790e3f9b 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -228,6 +228,28 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
        },
 
+       /* Xe2_HPM */
+
+       { XE_RTP_NAME("16021867713"),
+         XE_RTP_RULES(MEDIA_VERSION(1301),
+                      ENGINE_CLASS(VIDEO_DECODE)),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+       },
+       { XE_RTP_NAME("14020316580"),
+         XE_RTP_RULES(MEDIA_VERSION(1301)),
+         XE_RTP_ACTIONS(CLR(PG_ENABLE,
+                            VD0_HCP_POWERGATE_ENABLE |
+                            VD0_MFXVDENC_POWERGATE_ENABLE |
+                            VD2_HCP_POWERGATE_ENABLE |
+                            VD2_MFXVDENC_POWERGATE_ENABLE)),
+       },
+       { XE_RTP_NAME("14019449301"),
+         XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
+         XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
+         XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
+       },
+
        {}
 };
 
@@ -513,6 +535,16 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
        },
 
+       /* Xe2_HPM */
+
+       { XE_RTP_NAME("16021639441"),
+         XE_RTP_RULES(MEDIA_VERSION(1301)),
+         XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+                            GHWSP_CSB_REPORT_DIS |
+                            PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
+                            XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+       },
+
        {}
 };