drm/i915: Introduce plane->can_async_flip()

Move the "does this modifier support async flips?" check
to be handled by the platform specific plane code instead
of having a big mess in common code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241009182207.22900-4-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 48e657a80a16d90738345106ec8af10c8b3c6884..c46277e0d67d33543944a432d1590388642c5214 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -673,6 +673,11 @@ vlv_primary_disable_flip_done(struct intel_plane *plane)
        spin_unlock_irq(&i915->irq_lock);
 }
 
+static bool i9xx_plane_can_async_flip(u64 modifier)
+{
+       return modifier == I915_FORMAT_MOD_X_TILED;
+}
+
 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
                                    enum pipe *pipe)
 {
@@ -959,19 +964,23 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
                plane->async_flip = vlv_primary_async_flip;
                plane->enable_flip_done = vlv_primary_enable_flip_done;
                plane->disable_flip_done = vlv_primary_disable_flip_done;
+               plane->can_async_flip = i9xx_plane_can_async_flip;
        } else if (IS_BROADWELL(dev_priv)) {
                plane->need_async_flip_toggle_wa = true;
                plane->async_flip = g4x_primary_async_flip;
                plane->enable_flip_done = bdw_primary_enable_flip_done;
                plane->disable_flip_done = bdw_primary_disable_flip_done;
+               plane->can_async_flip = i9xx_plane_can_async_flip;
        } else if (DISPLAY_VER(dev_priv) >= 7) {
                plane->async_flip = g4x_primary_async_flip;
                plane->enable_flip_done = ivb_primary_enable_flip_done;
                plane->disable_flip_done = ivb_primary_disable_flip_done;
+               plane->can_async_flip = i9xx_plane_can_async_flip;
        } else if (DISPLAY_VER(dev_priv) >= 5) {
                plane->async_flip = g4x_primary_async_flip;
                plane->enable_flip_done = ilk_primary_enable_flip_done;
                plane->disable_flip_done = ilk_primary_disable_flip_done;
+               plane->can_async_flip = i9xx_plane_can_async_flip;
        }
 
        modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 612e9b0ec14abcd4f7bd67026d69b9d78f432e8f..5e0e074968671c0a11a072d98f6f77fc41326add 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -156,6 +156,11 @@ bool intel_plane_needs_physical(struct intel_plane *plane)
                DISPLAY_INFO(i915)->cursor_needs_physical;
 }
 
+bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier)
+{
+       return plane->can_async_flip && plane->can_async_flip(modifier);
+}
+
 unsigned int intel_adjusted_rate(const struct drm_rect *src,
                                 const struct drm_rect *dst,
                                 unsigned int rate)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 0f982f452ff391b5eed1380e2f0716943f14e80e..fb87b3353ab0d17ed1f1eb0197102147e812431a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -19,6 +19,7 @@ struct intel_plane;
 struct intel_plane_state;
 enum plane_id;
 
+bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier);
 unsigned int intel_adjusted_rate(const struct drm_rect *src,
                                 const struct drm_rect *dst,
                                 unsigned int rate);

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 210d52dc33fcfe9d1e21d382b30c35b20ad5d1f9..5ae0dea7b245c572097ffd09dd312af0cb3d17ed 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6528,58 +6528,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
                if (!plane->async_flip)
                        continue;
 
-               /*
-                * FIXME: This check is kept generic for all platforms.
-                * Need to verify this for all gen9 platforms to enable
-                * this selectively if required.
-                */
-               switch (new_plane_state->hw.fb->modifier) {
-               case DRM_FORMAT_MOD_LINEAR:
-                       /*
-                        * FIXME: Async on Linear buffer is supported on ICL as
-                        * but with additional alignment and fbc restrictions
-                        * need to be taken care of. These aren't applicable for
-                        * gen12+.
-                        */
-                       if (DISPLAY_VER(i915) < 12) {
-                               drm_dbg_kms(&i915->drm,
-                                           "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
-                                           plane->base.base.id, plane->base.name,
-                                           new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
-                               return -EINVAL;
-                       }
-                       break;
-               case I915_FORMAT_MOD_Y_TILED_CCS:
-               case I915_FORMAT_MOD_Yf_TILED_CCS:
-                       /*
-                        * Display WA #0731: skl
-                        * WaDisableRCWithAsyncFlip: skl
-                        * "When render decompression is enabled, hardware
-                        *  internally converts the Async flips to Sync flips."
-                        *
-                        * Display WA #1159: glk
-                        * "Async flip with render compression may result in
-                        *  intermittent underrun corruption."
-                        */
-                       if (DISPLAY_VER(i915) < 11) {
-                               drm_dbg_kms(&i915->drm,
-                                           "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
-                                           plane->base.base.id, plane->base.name,
-                                           new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
-                               return -EINVAL;
-                       }
-                       break;
-               case I915_FORMAT_MOD_X_TILED:
-               case I915_FORMAT_MOD_Y_TILED:
-               case I915_FORMAT_MOD_Yf_TILED:
-               case I915_FORMAT_MOD_4_TILED:
-               case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
-               case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
-               case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
-               case I915_FORMAT_MOD_4_TILED_BMG_CCS:
-               case I915_FORMAT_MOD_4_TILED_LNL_CCS:
-                       break;
-               default:
+               if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) {
                        drm_dbg_kms(&i915->drm,
                                    "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
                                    plane->base.base.id, plane->base.name,

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8271e50e36447a6c97a93ca0d0b83327ff6ee461..083eb86f090404131e065a66c10c8c25b236a244 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1474,6 +1474,7 @@ struct intel_plane {
        unsigned int (*max_stride)(struct intel_plane *plane,
                                   u32 pixel_format, u64 modifier,
                                   unsigned int rotation);
+       bool (*can_async_flip)(u64 modifier);
        /* Write all non-self arming plane registers */
        void (*update_noarm)(struct intel_dsb *dsb,
                             struct intel_plane *plane,

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 00ee7dfdeb5b85bfd1c813b2ac18b6ec1632f2fd..2679b446ab2b5a8abf4bbb4a44081b1647463751 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -516,6 +516,79 @@ skl_plane_max_stride(struct intel_plane *plane,
                                max_pixels, max_bytes);
 }
 
+static bool tgl_plane_can_async_flip(u64 modifier)
+{
+       switch (modifier) {
+       case DRM_FORMAT_MOD_LINEAR:
+       case I915_FORMAT_MOD_X_TILED:
+       case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_4_TILED:
+       case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+       case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+       case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+       case I915_FORMAT_MOD_4_TILED_BMG_CCS:
+       case I915_FORMAT_MOD_4_TILED_LNL_CCS:
+               return true;
+       case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+       case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
+       case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+       case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+       case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+       case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+               return false;
+       default:
+               return false;
+       }
+}
+
+static bool icl_plane_can_async_flip(u64 modifier)
+{
+       switch (modifier) {
+       case DRM_FORMAT_MOD_LINEAR:
+               /*
+                * FIXME: Async on Linear buffer is supported on ICL
+                * but with additional alignment and fbc restrictions
+                * need to be taken care of.
+                */
+               return false;
+       case I915_FORMAT_MOD_X_TILED:
+       case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_Yf_TILED:
+       case I915_FORMAT_MOD_Y_TILED_CCS:
+       case I915_FORMAT_MOD_Yf_TILED_CCS:
+               return true;
+       default:
+               return false;
+       }
+}
+
+static bool skl_plane_can_async_flip(u64 modifier)
+{
+       switch (modifier) {
+       case DRM_FORMAT_MOD_LINEAR:
+               return false;
+       case I915_FORMAT_MOD_X_TILED:
+       case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_Yf_TILED:
+               return true;
+       case I915_FORMAT_MOD_Y_TILED_CCS:
+       case I915_FORMAT_MOD_Yf_TILED_CCS:
+               /*
+                * Display WA #0731: skl
+                * WaDisableRCWithAsyncFlip: skl
+                * "When render decompression is enabled, hardware
+                *  internally converts the Async flips to Sync flips."
+                *
+                * Display WA #1159: glk
+                * "Async flip with render compression may result in
+                *  intermittent underrun corruption."
+                */
+               return false;
+       default:
+               return false;
+       }
+}
+
 static u32 tgl_plane_min_alignment(struct intel_plane *plane,
                                   const struct drm_framebuffer *fb,
                                   int color_plane)
@@ -2679,6 +2752,13 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
                plane->async_flip = skl_plane_async_flip;
                plane->enable_flip_done = skl_plane_enable_flip_done;
                plane->disable_flip_done = skl_plane_disable_flip_done;
+
+               if (DISPLAY_VER(dev_priv) >= 12)
+                       plane->can_async_flip = tgl_plane_can_async_flip;
+               else if (DISPLAY_VER(dev_priv) == 11)
+                       plane->can_async_flip = icl_plane_can_async_flip;
+               else
+                       plane->can_async_flip = skl_plane_can_async_flip;
        }
 
        if (DISPLAY_VER(dev_priv) >= 11)