soc: mediatek: Disable 9-bit alpha in ETHDR
authorHsiao Chien Sung <shawn.sung@mediatek.com>
Wed, 19 Jun 2024 16:50:24 +0000 (00:50 +0800)
committerAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Thu, 27 Jun 2024 10:41:51 +0000 (12:41 +0200)
When 9-bit alpha is enabled, its value will be converted from 0-255 to
0-256 (255 = not defined). This is designed for special HDR related
calculation, which should be disabled by default, otherwise, alpha
blending will not work correctly.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240620-9bit_alpha-v1-1-13c69daaf29f@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
drivers/soc/mediatek/mtk-mmsys.c

index f370f4ec4b88860036c34babd022ad85693c22a5..938240714e54c2b6c41e52bc92e31c73d9819bc3 100644 (file)
@@ -236,6 +236,7 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16
 
        mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
                              alpha << 16 | alpha, cmdq_pkt);
+       mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt);
        mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
                              alpha_sel << (19 + idx), cmdq_pkt);
        mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,