ASoC: amd: ps: add pci driver hw_ops for ACP7.0 & ACP7.1 variants
authorVijendar Mukunda <Vijendar.Mukunda@amd.com>
Fri, 7 Feb 2025 06:28:06 +0000 (11:58 +0530)
committerMark Brown <broonie@kernel.org>
Fri, 7 Feb 2025 13:33:48 +0000 (13:33 +0000)
Add below ACP pci driver hw_ops for ACP7.0 & ACP7.1 variants.
- acp_init()
- acp_deinit()
- acp_get_config()

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20250207062819.1527184-13-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/amd/ps/acp63.h
sound/soc/amd/ps/pci-ps.c
sound/soc/amd/ps/ps-common.c

index 098597d92bf9dcbe1680d62999b0caba1b093b9d..f65f242211e91d783c76b733172c76313e22509e 100644 (file)
@@ -12,6 +12,8 @@
 #define ACP63_REG_START                0x1240000
 #define ACP63_REG_END          0x125C000
 #define ACP63_PCI_REV          0x63
+#define ACP70_PCI_REV          0x70
+#define ACP71_PCI_REV          0x71
 
 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK  0x00010001
 #define ACP63_PGFSM_CNTL_POWER_ON_MASK 1
 
 #define ACP_HW_OPS(acp_data, cb)       ((acp_data)->hw_ops->cb)
 
+#define ACP70_PGFSM_CNTL_POWER_ON_MASK         0x1F
+#define ACP70_PGFSM_CNTL_POWER_OFF_MASK                0
+#define ACP70_PGFSM_STATUS_MASK                        0xFF
+#define ACP70_TIMEOUT                          2000
+#define ACP70_SDW_HOST_WAKE_MASK       0x0C00000
+
 enum acp_config {
        ACP_CONFIG_0 = 0,
        ACP_CONFIG_1,
@@ -149,6 +157,11 @@ enum acp_config {
        ACP_CONFIG_13,
        ACP_CONFIG_14,
        ACP_CONFIG_15,
+       ACP_CONFIG_16,
+       ACP_CONFIG_17,
+       ACP_CONFIG_18,
+       ACP_CONFIG_19,
+       ACP_CONFIG_20,
 };
 
 enum amd_acp63_sdw0_channel {
@@ -293,6 +306,7 @@ struct acp63_dev_data {
 };
 
 void acp63_hw_init_ops(struct acp_hw_ops *hw_ops);
+void acp70_hw_init_ops(struct acp_hw_ops *hw_ops);
 
 static inline int acp_hw_init(struct acp63_dev_data *adata, struct device *dev)
 {
index 04b43b4128bccb2355620286233c56dd5954f453..8f73d2ce21976d98084ad78cf8818caae49fd099 100644 (file)
@@ -438,6 +438,10 @@ static int acp_hw_init_ops(struct acp63_dev_data *adata, struct pci_dev *pci)
        case ACP63_PCI_REV:
                acp63_hw_init_ops(adata->hw_ops);
                break;
+       case ACP70_PCI_REV:
+       case ACP71_PCI_REV:
+               acp70_hw_init_ops(adata->hw_ops);
+               break;
        default:
                dev_err(&pci->dev, "ACP device not found\n");
                return -ENODEV;
@@ -460,12 +464,14 @@ static int snd_acp63_probe(struct pci_dev *pci,
        if (flag)
                return -ENODEV;
 
-       /* Pink Sardine device check */
+       /* ACP PCI revision id check for ACP6.3, ACP7.0 & ACP7.1 platforms */
        switch (pci->revision) {
        case ACP63_PCI_REV:
+       case ACP70_PCI_REV:
+       case ACP71_PCI_REV:
                break;
        default:
-               dev_dbg(&pci->dev, "acp63 pci device not found\n");
+               dev_dbg(&pci->dev, "acp63/acp70/acp71 pci device not found\n");
                return -ENODEV;
        }
        if (pci_enable_device(pci)) {
index 9098974b360807eaf630016c2dd715e66f93ba05..a15284bde48d9fdc284d92f1ba15b5f2946de5a4 100644 (file)
@@ -246,3 +246,141 @@ void acp63_hw_init_ops(struct acp_hw_ops *hw_ops)
        hw_ops->acp_suspend_runtime = snd_acp63_suspend;
        hw_ops->acp_resume_runtime = snd_acp63_runtime_resume;
 }
+
+static int acp70_power_on(void __iomem *acp_base)
+{
+       u32 val = 0;
+
+       val = readl(acp_base + ACP_PGFSM_STATUS);
+
+       if (!val)
+               return 0;
+       if (val & ACP70_PGFSM_STATUS_MASK)
+               writel(ACP70_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
+
+       return readl_poll_timeout(acp_base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP70_TIMEOUT);
+}
+
+static int acp70_reset(void __iomem *acp_base)
+{
+       u32 val;
+       int ret;
+
+       writel(1, acp_base + ACP_SOFT_RESET);
+
+       ret = readl_poll_timeout(acp_base + ACP_SOFT_RESET, val,
+                                val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK,
+                                DELAY_US, ACP70_TIMEOUT);
+       if (ret)
+               return ret;
+
+       writel(0, acp_base + ACP_SOFT_RESET);
+
+       return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP70_TIMEOUT);
+}
+
+static void acp70_enable_sdw_host_wake_interrupts(void __iomem *acp_base)
+{
+       u32 ext_intr_cntl1;
+
+       ext_intr_cntl1 = readl(acp_base + ACP_EXTERNAL_INTR_CNTL1);
+       ext_intr_cntl1 |= ACP70_SDW_HOST_WAKE_MASK;
+       writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
+}
+
+static void acp70_enable_interrupts(void __iomem *acp_base)
+{
+       u32 sdw0_wake_en, sdw1_wake_en;
+
+       writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
+       writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL);
+       sdw0_wake_en = readl(acp_base + ACP_SW0_WAKE_EN);
+       sdw1_wake_en = readl(acp_base + ACP_SW1_WAKE_EN);
+       if (sdw0_wake_en || sdw1_wake_en)
+               acp70_enable_sdw_host_wake_interrupts(acp_base);
+}
+
+static void acp70_disable_interrupts(void __iomem *acp_base)
+{
+       writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT);
+       writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
+       writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
+}
+
+static int acp70_init(void __iomem *acp_base, struct device *dev)
+{
+       int ret;
+
+       ret = acp70_power_on(acp_base);
+       if (ret) {
+               dev_err(dev, "ACP power on failed\n");
+               return ret;
+       }
+       writel(0x01, acp_base + ACP_CONTROL);
+       ret = acp70_reset(acp_base);
+       if (ret) {
+               dev_err(dev, "ACP reset failed\n");
+               return ret;
+       }
+       writel(0, acp_base + ACP_ZSC_DSP_CTRL);
+       acp70_enable_interrupts(acp_base);
+       writel(0x1, acp_base + ACP_PME_EN);
+       return 0;
+}
+
+static int acp70_deinit(void __iomem *acp_base, struct device *dev)
+{
+       int ret;
+
+       acp70_disable_interrupts(acp_base);
+       ret = acp70_reset(acp_base);
+       if (ret) {
+               dev_err(dev, "ACP reset failed\n");
+               return ret;
+       }
+       writel(0x01, acp_base + ACP_ZSC_DSP_CTRL);
+       return 0;
+}
+
+static void acp70_get_config(struct pci_dev *pci, struct acp63_dev_data *acp_data)
+{
+       u32 config;
+
+       config = readl(acp_data->acp63_base + ACP_PIN_CONFIG);
+       dev_dbg(&pci->dev, "ACP config value: %d\n", config);
+       switch (config) {
+       case ACP_CONFIG_4:
+       case ACP_CONFIG_5:
+       case ACP_CONFIG_10:
+       case ACP_CONFIG_11:
+       case ACP_CONFIG_20:
+               acp_data->is_pdm_config = true;
+               break;
+       case ACP_CONFIG_2:
+       case ACP_CONFIG_3:
+       case ACP_CONFIG_16:
+               acp_data->is_sdw_config = true;
+               break;
+       case ACP_CONFIG_6:
+       case ACP_CONFIG_7:
+       case ACP_CONFIG_12:
+       case ACP_CONFIG_8:
+       case ACP_CONFIG_13:
+       case ACP_CONFIG_14:
+       case ACP_CONFIG_17:
+       case ACP_CONFIG_18:
+       case ACP_CONFIG_19:
+               acp_data->is_pdm_config = true;
+               acp_data->is_sdw_config = true;
+               break;
+       default:
+               break;
+       }
+}
+
+void acp70_hw_init_ops(struct acp_hw_ops *hw_ops)
+{
+       hw_ops->acp_init = acp70_init;
+       hw_ops->acp_deinit = acp70_deinit;
+       hw_ops->acp_get_config = acp70_get_config;
+}