spi: spi-fsl-dspi: Reset SR flags before sending a new message

If, in a previous transfer, the controller sends more data than expected
by the DSPI target, SR.RFDF (RX FIFO is not empty) will remain asserted.
When flushing the FIFOs at the beginning of a new transfer (writing 1
into MCR.CLR_TXF and MCR.CLR_RXF), SR.RFDF should also be cleared.
Otherwise, when running in target mode with DMA, if SR.RFDF remains
asserted, the DMA callback will be fired before the controller sends any
data.

Take this opportunity to reset all Status Register fields.

Fixes: 5ce3cc567471 ("spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-3-bea884630cfb@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 1fa96e8189cfa1bc71d679d4e11546369fc93ced..863781ba6c1601f5d32cbf5a2d904374d33268b2 100644 (file)
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -975,6 +975,8 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr,
                                   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
                                   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 
+               regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
+
                spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
                                       dspi->progress, !dspi->irq);