drm/i915/display: update to plane_wm register access function

Future platforms can have new additions in the plane_wm
registers. So update skl_wm_level_from_reg_val() to have
possiblity for such platform differentiations. This is in
preparation for the rest of the patches in this series where
hw support for the minimum and interim ddb allocations for
async flip is added. Replace all the i915 uses to intel_display
in this function while updating this function

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-2-vinod.govindapillai@intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d93f6786db0ed3e767f0e3eabe0d8a0e8f6e6dcd..ea12476c0ff907272d248f70b31486c610e2b5a2 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2938,7 +2938,8 @@ skl_compute_wm(struct intel_atomic_state *state)
        return 0;
 }
 
-static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
+static void skl_wm_level_from_reg_val(struct intel_display *display,
+                                     u32 val, struct skl_wm_level *level)
 {
        level->enable = val & PLANE_WM_EN;
        level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
@@ -2950,7 +2951,6 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
                                     struct skl_pipe_wm *out)
 {
        struct intel_display *display = to_intel_display(crtc);
-       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
        enum pipe pipe = crtc->pipe;
        enum plane_id plane_id;
        int level;
@@ -2959,37 +2959,37 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
        for_each_plane_id_on_crtc(crtc, plane_id) {
                struct skl_plane_wm *wm = &out->planes[plane_id];
 
-               for (level = 0; level < i915->display.wm.num_levels; level++) {
+               for (level = 0; level < display->wm.num_levels; level++) {
                        if (plane_id != PLANE_CURSOR)
-                               val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level));
+                               val = intel_de_read(display, PLANE_WM(pipe, plane_id, level));
                        else
-                               val = intel_de_read(i915, CUR_WM(pipe, level));
+                               val = intel_de_read(display, CUR_WM(pipe, level));
 
-                       skl_wm_level_from_reg_val(val, &wm->wm[level]);
+                       skl_wm_level_from_reg_val(display, val, &wm->wm[level]);
                }
 
                if (plane_id != PLANE_CURSOR)
-                       val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id));
+                       val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id));
                else
-                       val = intel_de_read(i915, CUR_WM_TRANS(pipe));
+                       val = intel_de_read(display, CUR_WM_TRANS(pipe));
 
-               skl_wm_level_from_reg_val(val, &wm->trans_wm);
+               skl_wm_level_from_reg_val(display, val, &wm->trans_wm);
 
                if (HAS_HW_SAGV_WM(display)) {
                        if (plane_id != PLANE_CURSOR)
-                               val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id));
+                               val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id));
                        else
-                               val = intel_de_read(i915, CUR_WM_SAGV(pipe));
+                               val = intel_de_read(display, CUR_WM_SAGV(pipe));
 
-                       skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
+                       skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0);
 
                        if (plane_id != PLANE_CURSOR)
-                               val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id));
+                               val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id));
                        else
-                               val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe));
+                               val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe));
 
-                       skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
-               } else if (DISPLAY_VER(i915) >= 12) {
+                       skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm);
+               } else if (DISPLAY_VER(display) >= 12) {
                        wm->sagv.wm0 = wm->wm[0];
                        wm->sagv.trans_wm = wm->trans_wm;
                }