[
{
"BriefDescription": "Cycles L1D locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles L1D and L2 locked",
+ "Counter": "0,1",
"EventCode": "0x63",
"EventName": "CACHE_LOCK_CYCLES.L1D_L2",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1D cache lines replaced in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_EVICT",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1D cache lines allocated in the M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_REPL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1D snoop eviction of cache lines in M state",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.M_SNOOP_EVICT",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1 data cache lines allocated",
+ "Counter": "0,1",
"EventCode": "0x51",
"EventName": "L1D.REPL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1D prefetch load lock accepted in fill buffer",
+ "Counter": "0,1",
"EventCode": "0x52",
"EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "L1D hardware prefetch misses",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L1D hardware prefetch requests",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.REQUESTS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L1D hardware prefetch requests triggered",
+ "Counter": "0,1",
"EventCode": "0x4E",
"EventName": "L1D_PREFETCH.TRIGGERS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L1 writebacks to L2 in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.E_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L1 writebacks to L2 in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.I_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All L1 writebacks to L2",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.MESI",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L1 writebacks to L2 in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.M_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L1 writebacks to L2 in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "L1D_WB_L2.S_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All L2 data requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.ANY",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data demand loads in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data demand loads in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data demand requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.MESI",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data demand loads in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data demand loads in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data prefetches in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data prefetches in the I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "All L2 data prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data prefetches in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 data prefetches in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 lines allocated",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ANY",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 lines allocated in the E state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 lines allocated in the S state",
+ "Counter": "0,1,2,3",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 lines evicted",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.ANY",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 modified lines evicted by a demand request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 modified lines evicted by a prefetch request",
+ "Counter": "0,1,2,3",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 instruction fetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCHES",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 instruction fetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_HIT",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 instruction fetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.IFETCH_MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 load hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_HIT",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 load misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LD_MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.LOADS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "All L2 misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "All L2 prefetches",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCHES",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 prefetch hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_HIT",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 prefetch misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PREFETCH_MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "All L2 requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 RFO requests",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFOS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 RFO hits",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 RFO misses",
+ "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "All L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.ANY",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 fill transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.FILL",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 instruction fetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.IFETCH",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L1D writeback to L2 transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.L1D_WB",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 Load transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.LOAD",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 prefetch transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.PREFETCH",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 RFO transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.RFO",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 writeback to LLC transactions",
+ "Counter": "0,1,2,3",
"EventCode": "0xF0",
"EventName": "L2_TRANSACTIONS.WB",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "L2 demand lock RFOs in E state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.E_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All demand L2 lock RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.HIT",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand lock RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.I_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All demand L2 lock RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.MESI",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand lock RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.M_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand lock RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.LOCK.S_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All L2 demand store RFOs that hit the cache",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.HIT",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand store RFOs in I state (misses)",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.I_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "All L2 demand store RFOs",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.MESI",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand store RFOs in M state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.M_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "L2 demand store RFOs in S state",
+ "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "L2_WRITE.RFO.S_STATE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Longest latency cache miss",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Longest latency cache reference",
+ "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",
+ "Counter": "3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
"MSRIndex": "0x3F6",
},
{
"BriefDescription": "Instructions retired which contains a load (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.LOADS",
"PEBS": "1",
},
{
"BriefDescription": "Instructions retired which contains a store (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "MEM_INST_RETIRED.STORES",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.HIT_LFB",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L1D_HIT",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_MISS",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
"PEBS": "1",
},
{
"BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
"PEBS": "1",
},
{
"BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",
"PEBS": "1",
},
{
"BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",
"PEBS": "1",
},
{
"BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",
"PEBS": "1",
},
{
"BriefDescription": "Load instructions retired IO (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",
"PEBS": "1",
},
{
"BriefDescription": "All offcore requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.READ",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore RFO requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ANY.RFO",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore demand code read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore demand data read requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore demand RFO requests",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore L1 data cache writebacks",
+ "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Outstanding offcore reads",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles offcore reads busy",
+ "Counter": "0",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
},
{
"BriefDescription": "Outstanding offcore demand code reads",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles offcore demand code read busy",
+ "Counter": "0",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
},
{
"BriefDescription": "Outstanding offcore demand data reads",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles offcore demand data read busy",
+ "Counter": "0",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
},
{
"BriefDescription": "Outstanding offcore demand RFOs",
+ "Counter": "0",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles offcore demand RFOs busy",
+ "Counter": "0",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
},
{
"BriefDescription": "Offcore requests blocked due to Super Queue full",
+ "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_SQ_FULL",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Offcore data reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore writebacks",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore writebacks that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore code or data read requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore code or data read requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = any cache_dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = any location",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = local cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = local cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore request = all data, response = remote cache or dram",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore demand data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore demand data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore demand code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore demand RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore other requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore other requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore prefetch data requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore prefetch data reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore prefetch code reads",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore prefetch RFO requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "All offcore prefetch requests",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests that HIT in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Offcore prefetch requests that HITM in a remote cache",
+ "Counter": "2",
"EventCode": "0xB7",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
"MSRIndex": "0x1A6",
},
{
"BriefDescription": "Super Queue LRU hints sent to LLC",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.LRU_HINTS",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Super Queue lock splits across a cache line",
+ "Counter": "0,1,2,3",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Loads delayed with at-Retirement block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.AT_RET",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Cacheable loads delayed with L1D block code",
+ "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "STORE_BLOCKS.L1D_BLOCK",
"SampleAfterValue": "200000",
[
{
"BriefDescription": "Cycles the divider is busy",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Divide Operations executed",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x14",
},
{
"BriefDescription": "Multiply operations executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "BACLEAR asserted with bad target address",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "BACLEAR asserted, regardless of cause",
+ "Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Instruction queue forced BACLEAR",
+ "Counter": "0,1,2,3",
"EventCode": "0xA7",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Early Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Late Branch Prediction Unit clears",
+ "Counter": "0,1,2,3",
"EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Branch prediction unit missed call or return",
+ "Counter": "0,1,2,3",
"EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Branch instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Branch instructions executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Conditional branch instructions executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Unconditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Unconditional call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Indirect call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Indirect non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "All non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Indirect return branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Taken branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Retired branch instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
},
{
"BriefDescription": "Retired conditional branch instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "Retired near call instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
},
{
"BriefDescription": "Mispredicted branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Mispredicted conditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Mispredicted unconditional branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Mispredicted non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
},
{
"BriefDescription": "Mispredicted indirect call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
},
{
"BriefDescription": "Mispredicted indirect non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
},
{
"BriefDescription": "Mispredicted call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
},
{
"BriefDescription": "Mispredicted non call branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Mispredicted return branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
},
{
"BriefDescription": "Mispredicted taken branches executed",
+ "Counter": "0,1,2,3",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
},
{
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "Mispredicted near retired calls (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
},
{
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
+ "Counter": "Fixed counter 3",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
},
{
"BriefDescription": "Cycles when thread is not halted (fixed counter)",
+ "Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles when thread is not halted (programmable counter)",
+ "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Total CPU cycles",
+ "Counter": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
},
{
"BriefDescription": "Any Instruction Length Decoder stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Instruction Queue full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Length Change Prefix stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Stall cycles due to BPU MRU bypass",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Regen stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0x87",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Instructions that must be decoded by decoder 0",
+ "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Instructions written to instruction queue.",
+ "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles instructions are written to the instruction queue",
+ "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Instructions retired (fixed counter)",
+ "Counter": "Fixed counter 1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
},
{
"BriefDescription": "Retired MMX instructions (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.MMX",
"PEBS": "1",
},
{
"BriefDescription": "Total cycles (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
},
{
"BriefDescription": "Total cycles (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
},
{
"BriefDescription": "Retired floating-point operations (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PEBS": "1",
},
{
"BriefDescription": "Load operations conflicting with software prefetches",
+ "Counter": "0,1",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
},
{
"BriefDescription": "Cycles when uops were delivered by the LSD",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.ACTIVE",
},
{
"BriefDescription": "Cycles no uops were delivered by the LSD",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.INACTIVE",
},
{
"BriefDescription": "Loops that can't stream from the instruction queue",
+ "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles machine clear asserted",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "Self-Modifying Code detected",
+ "Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
},
{
"BriefDescription": "All RAT stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Flag stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Partial register stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "ROB read port stalls cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Scoreboard stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Resource related stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "FPU control word write stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Load buffer stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "MXCSR rename stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Other Resource related stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "ROB full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Reservation Station full stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Store buffer stall cycles",
+ "Counter": "0,1,2,3",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"PEBS": "1",
},
{
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"PEBS": "1",
},
{
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"PEBS": "1",
},
{
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"PEBS": "1",
},
{
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"PEBS": "1",
},
{
"BriefDescription": "Stack pointer instructions decoded",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Stack pointer sync operations",
+ "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Uops decoded by Microcode Sequencer",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
},
{
"BriefDescription": "Cycles no Uops are decoded",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xD1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
},
{
"BriefDescription": "Uops executed on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
},
{
"BriefDescription": "Uops executed on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xB1",
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
},
{
"BriefDescription": "Uops executed on port 0",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Uops issued on ports 0, 1 or 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
},
{
"BriefDescription": "Uops executed on port 1",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
{
"AnyThread": "1",
"BriefDescription": "Uops issued on ports 2, 3 or 4",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 2 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 3 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
{
"AnyThread": "1",
"BriefDescription": "Uops executed on port 4 (core count)",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Uops executed on port 5",
+ "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Uops issued",
+ "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
{
"AnyThread": "1",
"BriefDescription": "Cycles no Uops were issued on any thread",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles Uops were issued on either thread",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
},
{
"BriefDescription": "Fused Uops issued",
+ "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
},
{
"BriefDescription": "Cycles no Uops were issued",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xE",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
},
{
"BriefDescription": "Cycles Uops are being retired",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
},
{
"BriefDescription": "Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "1",
},
{
"BriefDescription": "Macro-fused Uops retired (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PEBS": "1",
},
{
"BriefDescription": "Retirement slots used (Precise Event)",
+ "Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
},
{
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
},
{
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
+ "Counter": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
},
{
"BriefDescription": "Uop unfusions due to FP exceptions",
+ "Counter": "0,1,2,3",
"EventCode": "0xDB",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
projects / linux-block.git / commitdiff