dt-bindings: clock: qcom: Add SA8775P video clock controller

Add device tree bindings for the video clock controller on Qualcomm
SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-1-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
new file mode 100644 (file)
index 0000000..928131b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SA8775P
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm video clock control module provides the clocks, resets and power
+  domains on SA8775P.
+
+  See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sa8775p-videocc
+
+  clocks:
+    items:
+      - description: Video AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep Clock source
+
+  power-domains:
+    maxItems: 1
+    description: MMCX power domain
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+    videocc: clock-controller@abf0000 {
+      compatible = "qcom,sa8775p-videocc";
+      reg = <0x0abf0000 0x10000>;
+      clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd SA8775P_MMCX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,sa8775p-videocc.h b/include/dt-bindings/clock/qcom,sa8775p-videocc.h
new file mode 100644 (file)
index 0000000..e6325f6
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sa8775p-videocc.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK                                       0
+#define VIDEO_CC_AHB_CLK_SRC                                   1
+#define VIDEO_CC_MVS0_CLK                                      2
+#define VIDEO_CC_MVS0_CLK_SRC                                  3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC                              4
+#define VIDEO_CC_MVS0C_CLK                                     5
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC                                6
+#define VIDEO_CC_MVS1_CLK                                      7
+#define VIDEO_CC_MVS1_CLK_SRC                                  8
+#define VIDEO_CC_MVS1_DIV_CLK_SRC                              9
+#define VIDEO_CC_MVS1C_CLK                                     10
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC                                11
+#define VIDEO_CC_PLL_LOCK_MONITOR_CLK                          12
+#define VIDEO_CC_SLEEP_CLK                                     13
+#define VIDEO_CC_SLEEP_CLK_SRC                                 14
+#define VIDEO_CC_SM_DIV_CLK_SRC                                        15
+#define VIDEO_CC_SM_OBS_CLK                                    16
+#define VIDEO_CC_XO_CLK                                                17
+#define VIDEO_CC_XO_CLK_SRC                                    18
+#define VIDEO_PLL0                                             19
+#define VIDEO_PLL1                                             20
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0C_GDSC                                    0
+#define VIDEO_CC_MVS0_GDSC                                     1
+#define VIDEO_CC_MVS1C_GDSC                                    2
+#define VIDEO_CC_MVS1_GDSC                                     3
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR                                 0
+#define VIDEO_CC_MVS0_BCR                                      1
+#define VIDEO_CC_MVS0C_CLK_ARES                                        2
+#define VIDEO_CC_MVS0C_BCR                                     3
+#define VIDEO_CC_MVS1_BCR                                      4
+#define VIDEO_CC_MVS1C_CLK_ARES                                        5
+#define VIDEO_CC_MVS1C_BCR                                     6
+
+#endif