drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX12

This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:

- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
  KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
  that requests are handled in a controlled manner and avoiding the
  race conditions.
- The CP (Compute Processor) firmware has been updated to use a private
  bus for accessing specific registers, avoiding unnecessary operations
  that could lead to issues in VF (Virtual Function) mode.
- The cleaner shader fence memory address is now set correctly in the
  `mes_set_hw_res_pkt` structure, allowing for proper synchronization of
  the cleaner shader execution.

Cc: Christian König <christian.koenig@amd.com>
Cc: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 901e924e69ad94813c64abccfcc3d0101132c641..4b8b4e8b9c40d213d914ead4218c2daf86c488c1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -678,6 +678,9 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
 
 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
 {
+       unsigned int alloc_size = AMDGPU_GPU_PAGE_SIZE;
+       int ret = 0;
+       struct amdgpu_device *adev = mes->adev;
        union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
 
        memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
@@ -687,6 +690,19 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
        mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
        mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 0xa;
 
+       ret = amdgpu_bo_create_kernel(adev, alloc_size, PAGE_SIZE,
+                               AMDGPU_GEM_DOMAIN_VRAM,
+                               &mes->resource_1,
+                               &mes->resource_1_gpu_addr,
+                               &mes->resource_1_addr);
+       if (ret) {
+               dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
+               return ret;
+       }
+
+       mes_set_hw_res_1_pkt.cleaner_shader_fence_mc_addr =
+               mes->resource_1_gpu_addr;
+
        return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe,
                        &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
                        offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
@@ -1761,6 +1777,12 @@ failure:
 
 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
 {
+       struct amdgpu_device *adev = ip_block->adev;
+
+       if (adev->enable_uni_mes)
+               amdgpu_bo_free_kernel(&adev->mes.resource_1,
+                                     &adev->mes.resource_1_gpu_addr,
+                                     &adev->mes.resource_1_addr);
        return 0;
 }