ARM: dts: stm32: Add alternate pinmux for ethernet0 pins

Add another mux option for ethernet0 pins, this is used on DHCOM when
the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and
then fed back via PA1 pin.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Christophe Roullier <christophe.roullier@foss.st.com>
Cc: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Tested-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index f0d66d8c6e3b3bff92fcc377c5acf3b919d040b6..4890e8d4353b98f5eaa228158d82a0be8f8d7ff1 100644 (file)
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -379,6 +379,40 @@
                };
        };
 
+       ethernet0_rmii_pins_c: rmii-2 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+                                <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+                                <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+                                <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
+                                <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
+                                <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
+                       bias-disable;
+                       drive-push-pull;
+                       slew-rate = <2>;
+               };
+               pins2 {
+                       pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */
+                                <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */
+                                <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */
+                       bias-disable;
+               };
+       };
+
+       ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
+               pins1 {
+                       pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+                                <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+                                <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+                                <STM32_PINMUX('A', 2, ANALOG)>,  /* ETH1_MDIO */
+                                <STM32_PINMUX('C', 1, ANALOG)>,  /* ETH1_MDC */
+                                <STM32_PINMUX('C', 4, ANALOG)>,  /* ETH1_RMII_RXD0 */
+                                <STM32_PINMUX('C', 5, ANALOG)>,  /* ETH1_RMII_RXD1 */
+                                <STM32_PINMUX('A', 1, ANALOG)>,  /* ETH1_RMII_REF_CLK */
+                                <STM32_PINMUX('A', 7, ANALOG)>;  /* ETH1_RMII_CRS_DV */
+               };
+       };
+
        fmc_pins_a: fmc-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */