Merge existing fixes from spi/for-6.1 into new branch
authorMark Brown <broonie@kernel.org>
Mon, 17 Oct 2022 11:47:33 +0000 (12:47 +0100)
committerMark Brown <broonie@kernel.org>
Mon, 17 Oct 2022 11:47:33 +0000 (12:47 +0100)
drivers/spi/spi-aspeed-smc.c
drivers/spi/spi-gxp.c
drivers/spi/spi-intel.c
drivers/spi/spi-mpc52xx.c
drivers/spi/spi-tegra210-quad.c
include/linux/spi/spi-mem.h

index a334e89add869e1c6fe0970e300ca8a3c8cc1937..33cefcf183927915935959530194a331c12c952e 100644 (file)
@@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = {
 static const struct aspeed_spi_data ast2600_fmc_data = {
        .max_cs        = 3,
        .hastype       = false,
-       .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
+       .mode_bits     = SPI_RX_QUAD | SPI_TX_QUAD,
        .we0           = 16,
        .ctl0          = CE0_CTRL_REG,
        .timing        = CE0_TIMING_COMPENSATION_REG,
@@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
 static const struct aspeed_spi_data ast2600_spi_data = {
        .max_cs        = 2,
        .hastype       = false,
-       .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
+       .mode_bits     = SPI_RX_QUAD | SPI_TX_QUAD,
        .we0           = 16,
        .ctl0          = CE0_CTRL_REG,
        .timing        = CE0_TIMING_COMPENSATION_REG,
index 15b11018383909763ddf45991c3bf61dd74d647d..c900c2f39b578f1d114249cb78d6831cc605e488 100644 (file)
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0=or-later
+// SPDX-License-Identifier: GPL-2.0-or-later
 /* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
 
 #include <linux/iopoll.h>
index 55f4ee2db002ce9d808e7e957b1018d78976c5f5..605acb1bf4b08e83c158c5871a1e3e8d8b7a9193 100644 (file)
 #define ERASE_OPCODE_SHIFT             8
 #define ERASE_OPCODE_MASK              (0xff << ERASE_OPCODE_SHIFT)
 #define ERASE_64K_OPCODE_SHIFT         16
-#define ERASE_64K_OPCODE_MASK          (0xff << ERASE_OPCODE_SHIFT)
+#define ERASE_64K_OPCODE_MASK          (0xff << ERASE_64K_OPCODE_SHIFT)
 
 /* Flash descriptor fields */
 #define FLVALSIG_MAGIC                 0x0ff0a55a
index cb075c1acbee30d5f931f6490c2bd8a8e44287e6..7b64e64c65cfec0bbe1f72bfa3e0dab270791632 100644 (file)
@@ -151,7 +151,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
        int spr, sppr;
        u8 ctrl1;
 
-       if (status && (irq != NO_IRQ))
+       if (status && irq)
                dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
                        status);
 
index c89592b21ffc5bcc6864e3465550cf4a9232da13..904972606bd45bb99a960b028ec5aef4c335c706 100644 (file)
@@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
                msg->actual_length += xfer->len;
                transfer_phase++;
        }
+       if (!xfer->cs_change) {
+               tegra_qspi_transfer_end(spi);
+               spi_transfer_delay_exec(xfer);
+       }
+       ret = 0;
 
 exit:
        msg->status = ret;
index 2ba044d0d5e5b984477248e5bafbc62475b8e109..8e984d75f5b6cae42735670090289006b307595f 100644 (file)
@@ -225,7 +225,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
 /**
  * struct spi_controller_mem_ops - SPI memory operations
  * @adjust_op_size: shrink the data xfer of an operation to match controller's
- *                 limitations (can be alignment of max RX/TX size
+ *                 limitations (can be alignment or max RX/TX size
  *                 limitations)
  * @supports_op: check if an operation is supported by the controller
  * @exec_op: execute a SPI memory operation