drm/i915/psr: vbt change for psr

For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not  mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version check
to change for all the platforms.

There is RCR inplace for GOP team to  provide the version number
to make generic change. Since Kabylake with bdb version 209 is having this
change, limiting this change to gen9_bc and version 209+ to unblock google.

Tested on skl(bdb version 203,without options) and
kabylake(bdb version 209,212) having new options.

bspec 20131

v2: (Jani and Rodrigo)
    move the 165 version check to intel_bios.c
v3: Jani
    Move the abstraction to intel_bios.
v4: Jani
    Rename tp*_wakeup_time to have "us" suffix.
    For values outside range[0-3],default to max 2500us.
    Old decimal value was wake up time in multiples of 100us.
v5: Jani and Rodrigo
    Handle option 2 in default condition.
    Print oustide range value.
    For negetive values default to 2500us.
v6: Jani
    Handle default first and then fall through for case 2.
v7: Rodrigo
    Apply this change for IS_GEN9_BC and vbt version > 209
v8: Puthik
    Add new function vbt_psr_to_us.
v9: Jani
    Change to v7 version as it's more readable.
    DK
    add comment /*fall through*/ after case2.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1526981243-2745-1-git-send-email-vathsala.nagaraju@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b8bd84f07995dc901fa18971d3462b95bf25fca..a7a563ed0fd8b9b5052ce50e969c206a90a63f4e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1077,8 +1077,8 @@ struct intel_vbt_data {
                bool require_aux_wakeup;
                int idle_frames;
                enum psr_lines_to_wait lines_to_wait;
-               int tp1_wakeup_time;
-               int tp2_tp3_wakeup_time;
+               int tp1_wakeup_time_us;
+               int tp2_tp3_wakeup_time_us;
        } psr;
 
        struct {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d52a11c2c73cbc23b66f3e202f011328d5b8905b..6953419881c4848dc39b47a9f84ddd33af543942 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4092,10 +4092,10 @@ enum {
 #define   EDP_Y_COORDINATE_ENABLE      (1<<25) /* GLK and CNL+ */
 #define   EDP_MAX_SU_DISABLE_TIME(t)   ((t)<<20)
 #define   EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
-#define   EDP_PSR2_TP2_TIME_500                (0<<8)
-#define   EDP_PSR2_TP2_TIME_100                (1<<8)
-#define   EDP_PSR2_TP2_TIME_2500       (2<<8)
-#define   EDP_PSR2_TP2_TIME_50         (3<<8)
+#define   EDP_PSR2_TP2_TIME_500us      (0<<8)
+#define   EDP_PSR2_TP2_TIME_100us      (1<<8)
+#define   EDP_PSR2_TP2_TIME_2500us     (2<<8)
+#define   EDP_PSR2_TP2_TIME_50us       (3<<8)
 #define   EDP_PSR2_TP2_TIME_MASK       (3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK        (0xf<<4)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 34c805970d7ce24b67bc1b7a9ab6870f5f8e472b..ea7ae8bc0ea0e3dd85a9bb4d11bc9ffbd9741a77 100644 (file)
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -684,8 +684,52 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
                break;
        }
 
-       dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time;
-       dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time;
+       /*
+        * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
+        * Old decimal value is wake up time in multiples of 100 us.
+        */
+       if (bdb->version >= 209 && IS_GEN9_BC(dev_priv)) {
+               switch (psr_table->tp1_wakeup_time) {
+               case 0:
+                       dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
+                       break;
+               case 1:
+                       dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
+                       break;
+               case 3:
+                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+                       break;
+               default:
+                       DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+                                       psr_table->tp1_wakeup_time);
+                       /* fallthrough */
+               case 2:
+                       dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
+                       break;
+               }
+
+               switch (psr_table->tp2_tp3_wakeup_time) {
+               case 0:
+                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
+                       break;
+               case 1:
+                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
+                       break;
+               case 3:
+                       dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
+                       break;
+               default:
+                       DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
+                                       psr_table->tp2_tp3_wakeup_time);
+                       /* fallthrough */
+               case 2:
+                       dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
+               break;
+               }
+       } else {
+               dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
+               dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
+       }
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1dec9034c75e88c2ce2683368615cb6..d64f03949d9ad454241b0ef7f6b40d26d6ab2655 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -461,23 +461,23 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
        if (dev_priv->psr.link_standby)
                val |= EDP_PSR_LINK_STANDBY;
 
-       if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
-               val |= EDP_PSR_TP1_TIME_2500us;
-       else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
-               val |= EDP_PSR_TP1_TIME_500us;
-       else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
+       if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
+               val |=  EDP_PSR_TP1_TIME_0us;
+       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
                val |= EDP_PSR_TP1_TIME_100us;
+       else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
+               val |= EDP_PSR_TP1_TIME_500us;
        else
-               val |= EDP_PSR_TP1_TIME_0us;
+               val |= EDP_PSR_TP1_TIME_2500us;
 
-       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-               val |= EDP_PSR_TP2_TP3_TIME_2500us;
-       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-               val |= EDP_PSR_TP2_TP3_TIME_500us;
-       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
+       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
+               val |=  EDP_PSR_TP2_TP3_TIME_0us;
+       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
                val |= EDP_PSR_TP2_TP3_TIME_100us;
+       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+               val |= EDP_PSR_TP2_TP3_TIME_500us;
        else
-               val |= EDP_PSR_TP2_TP3_TIME_0us;
+               val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
        if (intel_dp_source_supports_hbr2(intel_dp) &&
            drm_dp_tps3_supported(intel_dp->dpcd))
@@ -513,14 +513,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
        val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
-               val |= EDP_PSR2_TP2_TIME_2500;
-       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
-               val |= EDP_PSR2_TP2_TIME_500;
-       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
-               val |= EDP_PSR2_TP2_TIME_100;
+       if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
+           dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+               val |= EDP_PSR2_TP2_TIME_50us;
+       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+               val |= EDP_PSR2_TP2_TIME_100us;
+       else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+               val |= EDP_PSR2_TP2_TIME_500us;
        else
-               val |= EDP_PSR2_TP2_TIME_50;
+               val |= EDP_PSR2_TP2_TIME_2500us;
 
        I915_WRITE(EDP_PSR2_CTL, val);
 }