mutex_init(&adev->notifier_lock);
mutex_init(&adev->pm.stable_pstate_ctx_lock);
mutex_init(&adev->benchmark_mutex);
+ mutex_init(&adev->gfx.reset_sem_mutex);
amdgpu_device_init_apu_flags(adev);
}
static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,
- int req)
+ bool req)
{
u32 i, tmp, val;
+ if (req)
+ mutex_lock(&adev->gfx.reset_sem_mutex);
for (i = 0; i < adev->usec_timeout; i++) {
/* Request with MeId=2, PipeId=0 */
tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);
}
udelay(1);
}
+ if (!req)
+ mutex_unlock(&adev->gfx.reset_sem_mutex);
if (i >= adev->usec_timeout)
return -EINVAL;
mutex_unlock(&adev->srbm_mutex);
/* Try to acquire the gfx mutex before access to CP_VMID_RESET */
- r = gfx_v11_0_request_gfx_index_mutex(adev, 1);
+ r = gfx_v11_0_request_gfx_index_mutex(adev, true);
if (r) {
DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n");
return r;
RREG32_SOC15(GC, 0, regCP_VMID_RESET);
/* release the gfx mutex */
- r = gfx_v11_0_request_gfx_index_mutex(adev, 0);
+ r = gfx_v11_0_request_gfx_index_mutex(adev, false);
if (r) {
DRM_ERROR("Failed to release the gfx mutex during soft reset\n");
return r;