drm/msm: Fix bv_fence being used as bv_rptr
authorAntonino Maniscalco <antomani103@gmail.com>
Thu, 3 Oct 2024 16:12:50 +0000 (18:12 +0200)
committerRob Clark <robdclark@chromium.org>
Thu, 3 Oct 2024 20:18:34 +0000 (13:18 -0700)
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.

Add a bv_rptr field and change the code to use that instead.

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618010/
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
drivers/gpu/drm/msm/msm_ringbuffer.h

index 06cab2c6fd663b81d7f2c2bf4faf57104d2d574e..40a3d18c5b1ebcc8bb47b8c425790e06eb8316c4 100644 (file)
@@ -1129,7 +1129,7 @@ static int hw_init(struct msm_gpu *gpu)
        /* ..which means "always" on A7xx, also for BV shadow */
        if (adreno_is_a7xx(adreno_gpu)) {
                gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR,
-                           rbmemptr(gpu->rb[0], bv_fence));
+                           rbmemptr(gpu->rb[0], bv_rptr));
        }
 
        /* Always come up on rb 0 */
index 0d6beb8cd39a7b297e73741d2018915246a710d4..40791b2ade46ef0e16e2a4088291a575d3be9e82 100644 (file)
@@ -31,6 +31,7 @@ struct msm_rbmemptrs {
        volatile uint32_t rptr;
        volatile uint32_t fence;
        /* Introduced on A7xx */
+       volatile uint32_t bv_rptr;
        volatile uint32_t bv_fence;
 
        volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];