arm64: dts: exynos: configure GSCALER related clocks on TM2

GSCALER should be feed with clock at certain rates.  Configure it on
Exynos5433 based TM2 board.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index d88e2f0e179a96c632ffe30cb50e4c1852f9f5f1..d2de16645e101d13e5766ce8d7a20403f0406ec8 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -289,6 +289,12 @@
        assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
 };
 
+&cmu_mif {
+       assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
+       assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
+       assigned-clock-rates = <0>, <333000000>;
+};
+
 &cmu_mscl {
        assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
                          <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 3d7e0a782243df3033b0a14aa7d2387bba28fa0b..dda5d2746a74f6062e0ad5dc7dcab2dab0d71786 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -33,7 +33,8 @@
                          <&cmu_disp CLK_MOUT_DISP_PLL>,
                          <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
                          <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
-                         <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+                         <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
+                         <&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
        assigned-clock-parents = <0>, <0>,
                                 <&cmu_mif CLK_ACLK_DISP_333>,
                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
@@ -45,7 +46,8 @@
                                 <&cmu_disp CLK_FOUT_DISP_PLL>,
                                 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
-                                <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+                                <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+                                <&cmu_mif CLK_SCLK_DSD_DISP>;
        assigned-clock-rates = <250000000>, <400000000>;
 };