drm/amdgpu/sdma5: add mes queue fence handling

From IH ring buffer look up the coresponding kernel queue and process.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b73e455970312c6d3fe64cc970084afa1bb2b46a..564adc7b010c494895887bb4d994d28f764eca72 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1555,7 +1555,25 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
                                      struct amdgpu_irq_src *source,
                                      struct amdgpu_iv_entry *entry)
 {
+       uint32_t mes_queue_id = entry->src_data[0];
+
        DRM_DEBUG("IH: SDMA trap\n");
+
+       if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
+               struct amdgpu_mes_queue *queue;
+
+               mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
+
+               spin_lock(&adev->mes.queue_id_lock);
+               queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
+               if (queue) {
+                       DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
+                       amdgpu_fence_process(queue->ring);
+               }
+               spin_unlock(&adev->mes.queue_id_lock);
+               return 0;
+       }
+
        switch (entry->client_id) {
        case SOC15_IH_CLIENTID_SDMA0:
                switch (entry->ring_id) {