arm64: dts: ti: k3-am642-tqma64xxl-mbax4xxl: add PRU Ethernet support

Add PRU Ethernet controller and PHY nodes, as it was previously done for
the AM64x EVM Device Trees.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20240807121922.3180213-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index c40ad67cee0191989d267c9d34a9364b44917ca1..c2a62cb763a5937eba384bd9c1d25e480c76692b 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -24,6 +24,8 @@
 
        aliases {
                ethernet0 = &cpsw_port1;
+               ethernet1 = &icssg1_emac0;
+               ethernet2 = &icssg1_emac1;
                i2c1 = &mcu_i2c0;
                mmc1 = &sdhci1;
                serial0 = &mcu_uart0;
@@ -71,6 +73,66 @@
                };
        };
 
+       icssg1_eth: icssg1-eth {
+               compatible = "ti,am642-icssg-prueth";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>;
+               interrupt-parent = <&icssg1_intc>;
+               interrupts = <24 0 2>, <25 1 3>;
+               interrupt-names = "tx_ts0", "tx_ts1";
+               dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc201 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc202 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc203 15>, /* egress slice 0 */
+                      <&main_pktdma 0xc204 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc205 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc206 15>, /* egress slice 1 */
+                      <&main_pktdma 0xc207 15>, /* egress slice 1 */
+                      <&main_pktdma 0x4200 15>, /* ingress slice 0 */
+                      <&main_pktdma 0x4201 15>; /* ingress slice 1 */
+               dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+                           "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+                           "rx0", "rx1";
+               sram = <&oc_sram>;
+               firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
+                               "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
+                               "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
+                               "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
+                               "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
+                               "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
+               ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
+               ti,pruss-gp-mux-sel = <2>,      /* MII mode */
+                                     <2>,
+                                     <2>,
+                                     <2>,      /* MII mode */
+                                     <2>,
+                                     <2>;
+               ti,mii-g-rt = <&icssg1_mii_g_rt>;
+               ti,mii-rt = <&icssg1_mii_rt>;
+               ti,iep = <&icssg1_iep0>,  <&icssg1_iep1>;
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       icssg1_emac0: port@0 {
+                               reg = <0>;
+                               phy-handle = <&icssg1_phy0c>;
+                               phy-mode = "rgmii-id";
+                               /* Filled in by bootloader */
+                               local-mac-address = [00 00 00 00 00 00];
+                       };
+
+                       icssg1_emac1: port@1 {
+                               reg = <1>;
+                               phy-handle = <&icssg1_phy03>;
+                               phy-mode = "rgmii-id";
+                               /* Filled in by bootloader */
+                               local-mac-address = [00 00 00 00 00 00];
+                       };
+               };
+       };
+
        fan0: pwm-fan {
                compatible = "pwm-fan";
                pinctrl-names = "default";
@@ -154,6 +216,42 @@
        status = "okay";
 };
 
+&icssg1_mdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pru_icssg1_mdio_pins>;
+       status = "okay";
+
+       /* phy-mode is fixed up to rgmii-rxid by prueth driver to account for
+        * the SoC integration, so the only rx-internal-delay and no
+        * tx-internal-delay is set for the PHYs.
+        */
+
+       icssg1_phy03: ethernet-phy@3 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0x3>;
+               reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <1000>;
+               reset-deassert-us = <1000>;
+               ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+       };
+
+       icssg1_phy0c: ethernet-phy@c {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0xc>;
+               reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
+               reset-assert-us = <1000>;
+               reset-deassert-us = <1000>;
+               ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+       };
+};
+
+
 &main_gpio0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_gpio0_digital_pins>,