drm/xe/pvc: Force even num engines to use 64B
authorNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Tue, 18 Jul 2023 10:45:28 +0000 (10:45 +0000)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:40:27 +0000 (11:40 -0500)
Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/regs/xe_engine_regs.h
drivers/gpu/drm/xe/xe_wa.c

index 1a366d8070f39ac78d985543ab2f091bc7ae565d..692213d09ceaabb288bfbd00771c367ef54649a2 100644 (file)
@@ -64,6 +64,7 @@
 #define RING_BBADDR_UDW(base)                  XE_REG((base) + 0x168)
 
 #define BCS_SWCTRL(base)                       XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)
+#define   BCS_SWCTRL_DISABLE_256B              REG_BIT(2)
 
 /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
 #define BLIT_CCTL(base)                                XE_REG((base) + 0x204)
index e2b6e17d7ec4173e91537f421f6c38cd131b4226..f45e9452ba0eecaebe516f7b763c1cb42cacdb81 100644 (file)
@@ -604,6 +604,16 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
          XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))
        },
 
+       /* PVC */
+
+       { XE_RTP_NAME("16017236439"),
+         XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),
+                      FUNC(xe_rtp_match_even_instance)),
+         XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),
+                            BCS_SWCTRL_DISABLE_256B,
+                            XE_RTP_ACTION_FLAG(ENGINE_BASE))),
+       },
+
        /* Xe_LPG */
        { XE_RTP_NAME("18019271663"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),