arm64: dts: imx8mq-librem5: update pinctrl to match dtschema

The dtschema requires 'grp' in the end, so update the name.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index 7605802f294d799801e7ce08733432ae3174a19a..ce7ce2ba855c20bf0da60e6fcd36c05f781386b7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -667,7 +667,7 @@
                >;
        };
 
-       pinctrl_spkamp: spkamp {
+       pinctrl_spkamp: spkampgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3         0x81  /* MUTE */
                >;

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
index ceced6bc4e89852924f374c6fe21b607f958bed1..48d96183f3d18e078648b8019897ff228da578e8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
@@ -686,7 +686,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
@@ -703,7 +703,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
                        MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
@@ -733,7 +733,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x80
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK         0x8d
@@ -746,7 +746,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12        0x80
                        MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK         0x9f