net/mlx5: Query and cache PCAM, MCAM registers on initialization
authorGal Pressman <galp@mellanox.com>
Thu, 8 Dec 2016 14:03:31 +0000 (16:03 +0200)
committerSaeed Mahameed <saeedm@mellanox.com>
Thu, 19 Jan 2017 21:19:59 +0000 (23:19 +0200)
On load_one, we now cache our capabilities registers internally, similar
to QUERY_HCA_CAP. Capabilities can later be queried using macros
introduced in this patch.

Signed-off-by: Gal Pressman <galp@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/fw.c
include/linux/mlx5/device.h
include/linux/mlx5/driver.h

index 5718aada66055c9d439ccac237f287f834ab5a2c..d0bbefa08af78cac0b5b095ea283ab6e50ecd7e4 100644 (file)
@@ -91,6 +91,20 @@ out:
 }
 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
 
+static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
+{
+       return mlx5_query_pcam_reg(dev, dev->caps.pcam,
+                                  MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
+                                  MLX5_PCAM_REGS_5000_TO_507F);
+}
+
+static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
+{
+       return mlx5_query_mcam_reg(dev, dev->caps.mcam,
+                                  MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
+                                  MLX5_MCAM_REGS_FIRST_128);
+}
+
 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 {
        int err;
@@ -154,6 +168,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
                        return err;
        }
 
+       if (MLX5_CAP_GEN(dev, pcam_reg))
+               mlx5_get_pcam_reg(dev);
+
+       if (MLX5_CAP_GEN(dev, mcam_reg))
+               mlx5_get_mcam_reg(dev);
+
        return 0;
 }
 
index 79f38e67fe2f1ff3347c6aad5a4401dd50ae4a5e..f21528abfb748202ac01836a08b1d3717e30df2c 100644 (file)
@@ -1081,6 +1081,12 @@ enum mlx5_mcam_feature_groups {
 #define MLX5_CAP_QOS(mdev, cap)\
        MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
 
+#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
+       MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
+
+#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
+
 enum {
        MLX5_CMD_STAT_OK                        = 0x0,
        MLX5_CMD_STAT_INT_ERR                   = 0x1,
index 60c2b156da8cadbe844060378b0882b072c50ce5..69c4661d391e0b06b3673d5484f0622aa4cfd820 100644 (file)
@@ -739,6 +739,10 @@ struct mlx5_core_dev {
        struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
        u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
        u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
+       struct {
+               u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
+               u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
+       } caps;
        phys_addr_t             iseg_base;
        struct mlx5_init_seg __iomem *iseg;
        enum mlx5_device_state  state;