clk: tegra: Fix Tegra210 PLLU initialization

- Added necessary delays in PLLU enable sequence during initialization
- Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were
missing).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index fd04b0e501b7b757a3a822d8c8413c9c5d5f7b99..6d7a613f2656a4f8af55e0905a0c8c0daec6c0dc 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2554,6 +2554,7 @@ static int tegra210_enable_pllu(void)
        reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
        reg &= ~BIT(pllu.params->iddq_bit_idx);
        writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
+       udelay(5);
 
        reg = readl_relaxed(clk_base + PLLU_BASE);
        reg &= ~GENMASK(20, 0);
@@ -2561,6 +2562,7 @@ static int tegra210_enable_pllu(void)
        reg |= fentry->n << 8;
        reg |= fentry->p << 16;
        writel(reg, clk_base + PLLU_BASE);
+       udelay(1);
        reg |= PLL_ENABLE;
        writel(reg, clk_base + PLLU_BASE);
 
@@ -2800,14 +2802,14 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
        /* PLLU_60M */
        clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
                                CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
-                               23, 0, NULL);
+                               23, 0, &pll_u_lock);
        clk_register_clkdev(clk, "pll_u_60M", NULL);
        clks[TEGRA210_CLK_PLL_U_60M] = clk;
 
        /* PLLU_48M */
        clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
                                CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
-                               25, 0, NULL);
+                               25, 0, &pll_u_lock);
        clk_register_clkdev(clk, "pll_u_48M", NULL);
        clks[TEGRA210_CLK_PLL_U_48M] = clk;