drm/amd/display: Adjust incorrect indentations and spaces

This fixes indentations and adjust spaces for better readability and
code styles.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index dfaa200ecf1a508a811f543f08bb652585c85b9f..ab1132bc896a3264907dbdc3a0599ef8b9a2e559 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -83,7 +83,6 @@ CLK_MGR_DCN10 = rv1_clk_mgr.o rv1_clk_mgr_vbios_smu.o rv2_clk_mgr.o
 AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)
-
 ###############################################################################
 # DCN20
 ###############################################################################

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index d2abc00a60c5a571094db0bbe530147527bf4f76..0b2a3863b1f8696f5172584fb9d3795bdd4ac1c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -1539,7 +1539,6 @@ struct clk_mgr_internal *dcn401_clk_mgr_construct(
        }
 
        return &clk_mgr401->base;
-
 }
 
 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 518164dd9c3cc89467e12ab45158369fb4fe946f..1008fbc57dbd33c724e01977eb8f38b5738569c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1019,7 +1019,7 @@ static bool dc_construct(struct dc *dc,
                goto fail;
        }
 
-        dc_ctx = dc->ctx;
+       dc_ctx = dc->ctx;
 
        /* Resource should construct all asic specific resources.
         * This should be the only place where we need to parse the asic id
@@ -3361,10 +3361,10 @@ static void commit_planes_do_stream_update(struct dc *dc,
                                if (stream_update->mst_bw_update->is_increase)
                                        dc->link_srv->increase_mst_payload(pipe_ctx,
                                                        stream_update->mst_bw_update->mst_stream_bw);
-                               else
+                               else
                                        dc->link_srv->reduce_mst_payload(pipe_ctx,
                                                        stream_update->mst_bw_update->mst_stream_bw);
-                       }
+                       }
 
                        if (stream_update->pending_test_pattern) {
                                /*
@@ -3970,6 +3970,7 @@ static void commit_planes_for_stream(struct dc *dc,
 
        for (i = 0; i < surface_count; i++) {
                struct dc_plane_state *plane_state = srf_updates[i].surface;
+
                /*set logical flag for lock/unlock use*/
                for (j = 0; j < dc->res_pool->pipe_count; j++) {
                        struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
index e3be0bab4007b851803f130b5d1b3b4e694d351b..cd261051dc2c5703f0ca5b1a253f4746e15f3020 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
@@ -132,7 +132,7 @@
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
        DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
-       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
+       DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\
        DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
        DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
        DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 739298d2dff3b99a1ed296edd5d4a16fa6bdb117..b8996d285f003add60a0667f21920a878f9aec2c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -770,7 +770,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
                                                                        aux_defer_retries,
                                                                        AUX_MAX_RETRIES);
                                                goto fail;
-                                       } else 
+                                       } else
                                                udelay(300);
                                } else if (payload->write && ret > 0) {
                                        /* sink requested more time to complete the write via AUX_ACKM */
@@ -790,7 +790,6 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
                                        payload->write_status_update = true;
                                        payload->length = 0;
                                        udelay(300);
-
                                } else
                                        return true;
                        break;

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index ee601a6897a14dd2950d35d9bd2365cabd44a5f6..d28826c3ae5f1f9a7d0dd320cdabe4189006f65a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -298,12 +298,12 @@ static bool setup_engine(
        uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
        uint32_t  reset_length = 0;
 
-        if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
-            if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
-                    REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
-                    REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
-                    }
-            }
+       if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+               if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
+                       REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
+                       REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
+               }
+       }
 
        if (dce_i2c_hw->masks->DC_I2C_DDC1_CLK_EN)
                REG_UPDATE_N(SETUP, 1,

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 63ae4bc2a2e5cfa06bf7d200960cd407f49a4b53..f342da5a5e50f2a7819ae684d9f9444842e6602b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -575,7 +575,6 @@ static void dce60_opp_program_clamping_and_pixel_encoding(
 }
 #endif
 
-
 static void program_formatter_420_memory(struct output_pixel_processor *opp)
 {
        struct dce110_opp *opp110 = TO_DCE110_OPP(opp);

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index f810825322ba9fca922695688a7829d425a44ab8..5c2825bc9a87664424444e6e006eb8bd6c328b67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -1025,6 +1025,7 @@ static void dce110_reset_hdmi_stream_attribute(
        struct stream_encoder *enc)
 {
        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+
        if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
                REG_UPDATE_5(HDMI_CONTROL,
                        HDMI_PACKET_GEN_VERSION, 1,

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 4f559a025cf005e6f4ad8d3cca6e23ec3a774ca1..2873ac8f16fbbf4df0b2fbf82977385e97e6e4c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -109,7 +109,6 @@ static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait,
                if (retry_count >= 1000)
                        ASSERT(0);
        }
-
 }
 
 /*

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index c34e04cac9a06e3080a84dda2c9c7ac2ddce6621..762c579fcb44dd6423eb1071f625c81566303396 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -282,7 +282,6 @@ struct mpll_cfg {
        uint32_t tx_peaking_lvl;
        uint32_t ctr_reqs_pll;
 
-
 };
 
 struct dpcssys_phy_seq_cfg {