arm64: dts: mediatek: mt8188: Add display nodes for vdosys0

Add the vdosys0 display nodes to support the internal display pipeline.

Signed-off-by: Fei Shao <fshao@chromium.org>
Link: https://lore.kernel.org/r/20241014111053.2294519-7-fshao@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index facd4ed57754903144bee4c99788c37743a62495..995b2e712c888d9ff5c014b39e268633fbb392ab 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -26,6 +26,7 @@
        aliases {
                gce0 = &gce0;
                gce1 = &gce1;
+               mutex0 = &mutex0;
        };
 
        cpus {
@@ -2361,6 +2362,71 @@
                        power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
                };
 
+               ovl0: ovl@1c000000 {
+                       compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl";
+                       reg = <0 0x1c000000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+                       interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+                       iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
+               };
+
+               rdma0: rdma@1c002000 {
+                       compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
+                       reg = <0 0x1c002000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+                       interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+                       iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
+               };
+
+               color0: color@1c003000 {
+                       compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
+                       reg = <0 0x1c003000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+                       interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
+               };
+
+               ccorr0: ccorr@1c004000 {
+                       compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
+                       reg = <0 0x1c004000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+                       interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
+               };
+
+               aal0: aal@1c005000 {
+                       compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
+                       reg = <0 0x1c005000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+                       interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
+               };
+
+               gamma0: gamma@1c006000 {
+                       compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
+                       reg = <0 0x1c006000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+                       interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
+               };
+
+               dither0: dither@1c007000 {
+                       compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
+                       reg = <0 0x1c007000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+                       interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
+               };
+
                disp_dsi0: dsi@1c008000 {
                        compatible = "mediatek,mt8188-dsi";
                        reg = <0 0x1c008000 0 0x1000>;
@@ -2391,6 +2457,26 @@
                        status = "disabled";
                };
 
+               mutex0: mutex@1c016000 {
+                       compatible = "mediatek,mt8188-disp-mutex";
+                       reg = <0 0x1c016000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+                       interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+               };
+
+               postmask0: postmask@1c01a000 {
+                       compatible = "mediatek,mt8188-disp-postmask",
+                                    "mediatek,mt8192-disp-postmask";
+                       reg = <0 0x1c01a000 0 0x1000>;
+                       clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>;
+                       interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+                       mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
+               };
+
                vdosys0: syscon@1c01d000 {
                        compatible = "mediatek,mt8188-vdosys0", "syscon";
                        reg = <0 0x1c01d000 0 0x1000>;