drm/i915: Set SSC frequency for 8xx chips correctly
authorling.ma@intel.com <ling.ma@intel.com>
Thu, 25 Jun 2009 02:59:22 +0000 (10:59 +0800)
committerEric Anholt <eric@anholt.net>
Wed, 1 Jul 2009 18:20:44 +0000 (11:20 -0700)
All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/intel_bios.c

index 716409a57244b710684deb66e59f11ed3b0dc81e..da22863c05c0a89e4874fd55b85c71953158ab1a 100644 (file)
@@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
                dev_priv->lvds_use_ssc = general->enable_ssc;
 
                if (dev_priv->lvds_use_ssc) {
-                 if (IS_I855(dev_priv->dev))
-                   dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
-                 else
-                   dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+                       if (IS_I85X(dev_priv->dev))
+                               dev_priv->lvds_ssc_freq =
+                                       general->ssc_freq ? 66 : 48;
+                       else
+                               dev_priv->lvds_ssc_freq =
+                                       general->ssc_freq ? 100 : 96;
                }
        }
 }