arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields

In preparation for converting the ID_AA64MMFR1_EL1 system register
defines to automatic generation, rename them to follow the conventions
used by other automatically generated registers:

 * Add _EL1 in the register name.

 * Rename fields to match the names in the ARM ARM:
   * LOR -> LO
   * HPD -> HPDS
   * VHE -> VH
   * HADBS -> HAFDBS
   * SPECSEI -> SpecSEI
   * VMIDBITS -> VMIDBits

There should be no functional change as a result of this patch.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-11-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index d7b96dc9364b128e4decfcf2b19f281481cad287..5fc43f7f3ed609892bea63deb6b456486e11faed 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -868,14 +868,14 @@ static inline bool cpu_has_hw_af(void)
 
        mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
        return cpuid_feature_extract_unsigned_field(mmfr1,
-                                               ID_AA64MMFR1_HADBS_SHIFT);
+                                               ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
 }
 
 static inline bool cpu_has_pan(void)
 {
        u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
        return cpuid_feature_extract_unsigned_field(mmfr1,
-                                                   ID_AA64MMFR1_PAN_SHIFT);
+                                                   ID_AA64MMFR1_EL1_PAN_SHIFT);
 }
 
 #ifdef CONFIG_ARM64_AMU_EXTN
@@ -896,8 +896,8 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
        int vmid_bits;
 
        vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
-                                               ID_AA64MMFR1_VMIDBITS_SHIFT);
-       if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)
+                                               ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
+       if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
                return 16;
 
        /*

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 80ef55b6619623a19bc1a46e956efbe6d868c7ce..b6e9bea7c9ec6f356513a3cceceef99d0122d49d 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -83,7 +83,7 @@
 /* LORegions */
 .macro __init_el2_lor
        mrs     x1, id_aa64mmfr1_el1
-       ubfx    x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
+       ubfx    x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
        cbz     x0, .Lskip_lor_\@
        msr_s   SYS_LORC_EL1, xzr
 .Lskip_lor_\@:

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b6cd9996e12b9f3e61afa72f50155ae941d446f0..410b628fbb679096a61a4137a37f14384bb1aa41 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -783,26 +783,26 @@
 #endif
 
 /* id_aa64mmfr1 */
-#define ID_AA64MMFR1_ECBHB_SHIFT       60
-#define ID_AA64MMFR1_TIDCP1_SHIFT      52
-#define ID_AA64MMFR1_HCX_SHIFT         40
-#define ID_AA64MMFR1_AFP_SHIFT         44
-#define ID_AA64MMFR1_ETS_SHIFT         36
-#define ID_AA64MMFR1_TWED_SHIFT                32
-#define ID_AA64MMFR1_XNX_SHIFT         28
-#define ID_AA64MMFR1_SPECSEI_SHIFT     24
-#define ID_AA64MMFR1_PAN_SHIFT         20
-#define ID_AA64MMFR1_LOR_SHIFT         16
-#define ID_AA64MMFR1_HPD_SHIFT         12
-#define ID_AA64MMFR1_VHE_SHIFT         8
-#define ID_AA64MMFR1_VMIDBITS_SHIFT    4
-#define ID_AA64MMFR1_HADBS_SHIFT       0
-
-#define ID_AA64MMFR1_VMIDBITS_8                0
-#define ID_AA64MMFR1_VMIDBITS_16       2
-
-#define ID_AA64MMFR1_TIDCP1_NI         0
-#define ID_AA64MMFR1_TIDCP1_IMP                1
+#define ID_AA64MMFR1_EL1_ECBHB_SHIFT           60
+#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT          52
+#define ID_AA64MMFR1_EL1_HCX_SHIFT             40
+#define ID_AA64MMFR1_EL1_AFP_SHIFT             44
+#define ID_AA64MMFR1_EL1_ETS_SHIFT             36
+#define ID_AA64MMFR1_EL1_TWED_SHIFT            32
+#define ID_AA64MMFR1_EL1_XNX_SHIFT             28
+#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT         24
+#define ID_AA64MMFR1_EL1_PAN_SHIFT             20
+#define ID_AA64MMFR1_EL1_LO_SHIFT              16
+#define ID_AA64MMFR1_EL1_HPDS_SHIFT            12
+#define ID_AA64MMFR1_EL1_VH_SHIFT              8
+#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT                4
+#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT          0
+
+#define ID_AA64MMFR1_EL1_VMIDBits_8            0
+#define ID_AA64MMFR1_EL1_VMIDBits_16           2
+
+#define ID_AA64MMFR1_EL1_TIDCP1_NI             0
+#define ID_AA64MMFR1_EL1_TIDCP1_IMP            1
 
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_EL1_E0PD_SHIFT    60

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index ba44f67c5544d1f7c3866806e94670e30086cfdc..534819afadd5702c331bece8de722a9a9259c5d7 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -362,18 +362,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2116,7 +2116,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .matches = has_cpuid_feature,
                .sys_reg = SYS_ID_AA64MMFR1_EL1,
-               .field_pos = ID_AA64MMFR1_PAN_SHIFT,
+               .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
                .field_width = 4,
                .sign = FTR_UNSIGNED,
                .min_field_value = 1,
@@ -2130,7 +2130,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .matches = has_cpuid_feature,
                .sys_reg = SYS_ID_AA64MMFR1_EL1,
-               .field_pos = ID_AA64MMFR1_PAN_SHIFT,
+               .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
                .field_width = 4,
                .sign = FTR_UNSIGNED,
                .min_field_value = 3,
@@ -2344,7 +2344,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .capability = ARM64_HW_DBM,
                .sys_reg = SYS_ID_AA64MMFR1_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
+               .field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
                .field_width = 4,
                .min_field_value = 2,
                .matches = has_hw_dbm,
@@ -2614,9 +2614,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .sys_reg = SYS_ID_AA64MMFR1_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64MMFR1_TIDCP1_SHIFT,
+               .field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,
                .field_width = 4,
-               .min_field_value = ID_AA64MMFR1_TIDCP1_IMP,
+               .min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,
                .matches = has_cpuid_feature,
                .cpu_enable = cpu_trap_el0_impdef,
        },
@@ -2752,7 +2752,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
        HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
 #endif /* CONFIG_ARM64_MTE */
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
-       HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+       HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
 #ifdef CONFIG_ARM64_SME

diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index bce1f5f6b8c9ecd685a80f05dba9e2dedb707007..2ee18c860f2ab61de44444c7faa5ec77de7b3ca4 100644 (file)
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -142,7 +142,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
        msr_s   SYS_SMPRIMAP_EL2, xzr           // Make all priorities equal
 
        mrs     x1, id_aa64mmfr1_el1            // HCRX_EL2 present?
-       ubfx    x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
+       ubfx    x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
        cbz     x1, .Lskip_sme
 
        mrs_s   x1, SYS_HCRX_EL2
@@ -157,7 +157,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
        tbnz    x1, #0, 1f
 
        // Needs to be VHE capable, obviously
-       check_override id_aa64mmfr1 ID_AA64MMFR1_VHE_SHIFT 2f 1f
+       check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
 
 1:     mov_q   x0, HVC_STUB_ERR
        eret

diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c
index 8c474915a11d8f6b1ee9897614474bdf10a670ad..95133765ed29a0e4f9c68e1fecfb9d9332034454 100644 (file)
--- a/arch/arm64/kernel/idreg-override.c
+++ b/arch/arm64/kernel/idreg-override.c
@@ -50,7 +50,7 @@ static const struct ftr_set_desc mmfr1 __initconst = {
        .name           = "id_aa64mmfr1",
        .override       = &id_aa64mmfr1_override,
        .fields         = {
-               FIELD("vh", ID_AA64MMFR1_VHE_SHIFT, mmfr1_vh_filter),
+               FIELD("vh", ID_AA64MMFR1_EL1_VH_SHIFT, mmfr1_vh_filter),
                {}
        },
 };

diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
index 6ee586b4e235c590e569f1b179168103b03998d9..fe3bc4c1c5acbad023f4181bc4e5f1e1a4d2f41a 100644 (file)
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@ -945,7 +945,7 @@ static bool supports_ecbhb(int scope)
                mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
 
        return cpuid_feature_extract_unsigned_field(mmfr1,
-                                                   ID_AA64MMFR1_ECBHB_SHIFT);
+                                                   ID_AA64MMFR1_EL1_ECBHB_SHIFT);
 }
 
 bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry,

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 0c2e474d0c9e7c63e7dd24f757dde9feb6f5b9d1..1653299ff8f872f084ffbc773b3134b5c9db848f 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -100,12 +100,12 @@
  * - Enhanced Translation Synchronization
  */
 #define PVM_ID_AA64MMFR1_ALLOW (\
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_HADBS) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_VMIDBITS) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_HPD) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_PAN) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_SPECSEI) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR1_ETS) \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
        )
 
 /*

diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 05301d3b3fc20294d94030e1ebdd1e088d3950ee..b92ecdd6bdab27e246b67d356bcaa45e7206821b 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -143,7 +143,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
        u64 hcr_set = 0;
 
        /* Trap LOR */
-       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_LOR), feature_ids))
+       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids))
                hcr_set |= HCR_TLOR;
 
        vcpu->arch.hcr_el2 |= hcr_set;

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ff4405a6ea253c53ffae93b5cd65172a2f6c9b12..fa61793467a735840e58de98c08ac493d139152c 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -273,7 +273,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
        u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
        u32 sr = reg_to_encoding(r);
 
-       if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
+       if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
                kvm_inject_undefined(vcpu);
                return false;
        }