dcn30_cm_common.o \
dcn30_mmhubbub.o \
-
-
AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_DCN30)
# Makefile for dcn31.
DCN31 = dcn31_panel_cntl.o \
- dcn31_apg.o dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o \
+ dcn31_apg.o \
dcn31_afmt.o dcn31_vpg.o
AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31))
+++ /dev/null
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dc_bios_types.h"
-#include "dcn31_hpo_dp_link_encoder.h"
-#include "reg_helper.h"
-#include "stream_encoder.h"
-
-#define DC_LOGGER \
- enc3->base.ctx->logger
-
-#define REG(reg)\
- (enc3->regs->reg)
-
-#undef FN
-#define FN(reg_name, field_name) \
- enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name
-
-
-#define CTX \
- enc3->base.ctx
-
-enum {
- DP_SAT_UPDATE_MAX_RETRY = 200
-};
-
-void dcn31_hpo_dp_link_enc_enable(
- struct hpo_dp_link_encoder *enc,
- enum dc_lane_count num_lanes)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- uint32_t dp_link_enabled;
-
- /* get current status of link enabled */
- REG_GET(DP_DPHY_SYM32_STATUS,
- STATUS, &dp_link_enabled);
-
- /* Enable clocks first */
- REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 1);
-
- /* Reset DPHY. Only reset if going from disable to enable */
- if (!dp_link_enabled) {
- REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 1);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 0);
- }
-
- /* Configure DPHY settings */
- REG_UPDATE_3(DP_DPHY_SYM32_CONTROL,
- DPHY_ENABLE, 1,
- PRECODER_ENABLE, 1,
- NUM_LANES, num_lanes == LANE_COUNT_ONE ? 0 : num_lanes == LANE_COUNT_TWO ? 1 : 3);
-}
-
-void dcn31_hpo_dp_link_enc_disable(
- struct hpo_dp_link_encoder *enc)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
-
- /* Configure DPHY settings */
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- DPHY_ENABLE, 0);
-
- /* Shut down clock last */
- REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 0);
-}
-
-void dcn31_hpo_dp_link_enc_set_link_test_pattern(
- struct hpo_dp_link_encoder *enc,
- struct encoder_set_dp_phy_pattern_param *tp_params)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- uint32_t tp_custom;
-
- switch (tp_params->dp_phy_pattern) {
- case DP_TEST_PATTERN_VIDEO_MODE:
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_LINK_ACTIVE);
- break;
- case DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE:
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_LINK_TRAINING_TPS1);
- break;
- case DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE:
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_LINK_TRAINING_TPS2);
- break;
- case DP_TEST_PATTERN_128b_132b_TPS1:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_TPS1,
- TP_SELECT1, DP_DPHY_TP_SELECT_TPS1,
- TP_SELECT2, DP_DPHY_TP_SELECT_TPS1,
- TP_SELECT3, DP_DPHY_TP_SELECT_TPS1);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_128b_132b_TPS2:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_TPS2,
- TP_SELECT1, DP_DPHY_TP_SELECT_TPS2,
- TP_SELECT2, DP_DPHY_TP_SELECT_TPS2,
- TP_SELECT3, DP_DPHY_TP_SELECT_TPS2);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS7:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS7,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS7,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS7,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS7);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS9:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS9,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS9,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS9,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS9);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS11:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS11,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS11,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS11,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS11);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS15:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS15,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS15,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS15,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS15);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS23:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS23,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS23,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS23,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS23);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_PRBS31:
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_PRBS_SEL0, DP_DPHY_TP_PRBS31,
- TP_PRBS_SEL1, DP_DPHY_TP_PRBS31,
- TP_PRBS_SEL2, DP_DPHY_TP_PRBS31,
- TP_PRBS_SEL3, DP_DPHY_TP_PRBS31);
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
- TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_264BIT_CUSTOM:
- tp_custom = (tp_params->custom_pattern[2] << 16) | (tp_params->custom_pattern[1] << 8) | tp_params->custom_pattern[0];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[5] << 16) | (tp_params->custom_pattern[4] << 8) | tp_params->custom_pattern[3];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[8] << 16) | (tp_params->custom_pattern[7] << 8) | tp_params->custom_pattern[6];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[11] << 16) | (tp_params->custom_pattern[10] << 8) | tp_params->custom_pattern[9];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[14] << 16) | (tp_params->custom_pattern[13] << 8) | tp_params->custom_pattern[12];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[17] << 16) | (tp_params->custom_pattern[16] << 8) | tp_params->custom_pattern[15];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[20] << 16) | (tp_params->custom_pattern[19] << 8) | tp_params->custom_pattern[18];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[23] << 16) | (tp_params->custom_pattern[22] << 8) | tp_params->custom_pattern[21];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[26] << 16) | (tp_params->custom_pattern[25] << 8) | tp_params->custom_pattern[24];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[29] << 16) | (tp_params->custom_pattern[28] << 8) | tp_params->custom_pattern[27];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM9, 0, TP_CUSTOM, tp_custom);
- tp_custom = (tp_params->custom_pattern[32] << 16) | (tp_params->custom_pattern[31] << 8) | tp_params->custom_pattern[30];
- REG_SET(DP_DPHY_SYM32_TP_CUSTOM10, 0, TP_CUSTOM, tp_custom);
-
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_CUSTOM,
- TP_SELECT1, DP_DPHY_TP_SELECT_CUSTOM,
- TP_SELECT2, DP_DPHY_TP_SELECT_CUSTOM,
- TP_SELECT3, DP_DPHY_TP_SELECT_CUSTOM);
-
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- case DP_TEST_PATTERN_SQUARE:
- case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:
- case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:
- case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:
- REG_SET(DP_DPHY_SYM32_TP_SQ_PULSE, 0,
- TP_SQ_PULSE_WIDTH, tp_params->custom_pattern[0]);
-
- REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
- TP_SELECT0, DP_DPHY_TP_SELECT_SQUARE,
- TP_SELECT1, DP_DPHY_TP_SELECT_SQUARE,
- TP_SELECT2, DP_DPHY_TP_SELECT_SQUARE,
- TP_SELECT3, DP_DPHY_TP_SELECT_SQUARE);
-
- REG_UPDATE(DP_DPHY_SYM32_CONTROL,
- MODE, DP2_TEST_PATTERN);
- break;
- default:
- break;
- }
-}
-
-static void fill_stream_allocation_row_info(
- const struct link_mst_stream_allocation *stream_allocation,
- uint32_t *src,
- uint32_t *slots)
-{
- const struct hpo_dp_stream_encoder *stream_enc = stream_allocation->hpo_dp_stream_enc;
-
- if (stream_enc && (stream_enc->id >= ENGINE_ID_HPO_DP_0)) {
- *src = stream_enc->id - ENGINE_ID_HPO_DP_0;
- *slots = stream_allocation->slot_count;
- } else {
- *src = 0;
- *slots = 0;
- }
-}
-
-/* programs DP VC payload allocation */
-void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
- struct hpo_dp_link_encoder *enc,
- const struct link_mst_stream_allocation_table *table)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- uint32_t slots = 0;
- uint32_t src = 0;
-
- /* --- Set MSE Stream Attribute -
- * Setup VC Payload Table on Tx Side,
- * Issue allocation change trigger
- * to commit payload on both tx and rx side
- */
-
- /* we should clean-up table each time */
-
- if (table->stream_count >= 1) {
- fill_stream_allocation_row_info(
- &table->stream_allocations[0],
- &src,
- &slots);
- } else {
- src = 0;
- slots = 0;
- }
-
- REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC0,
- SAT_STREAM_SOURCE, src,
- SAT_SLOT_COUNT, slots);
-
- if (table->stream_count >= 2) {
- fill_stream_allocation_row_info(
- &table->stream_allocations[1],
- &src,
- &slots);
- } else {
- src = 0;
- slots = 0;
- }
-
- REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC1,
- SAT_STREAM_SOURCE, src,
- SAT_SLOT_COUNT, slots);
-
- if (table->stream_count >= 3) {
- fill_stream_allocation_row_info(
- &table->stream_allocations[2],
- &src,
- &slots);
- } else {
- src = 0;
- slots = 0;
- }
-
- REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC2,
- SAT_STREAM_SOURCE, src,
- SAT_SLOT_COUNT, slots);
-
- if (table->stream_count >= 4) {
- fill_stream_allocation_row_info(
- &table->stream_allocations[3],
- &src,
- &slots);
- } else {
- src = 0;
- slots = 0;
- }
-
- REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC3,
- SAT_STREAM_SOURCE, src,
- SAT_SLOT_COUNT, slots);
-
- /* --- wait for transaction finish */
-
- /* send allocation change trigger (ACT)
- * this step first sends the ACT,
- * then double buffers the SAT into the hardware
- * making the new allocation active on the DP MST mode link
- */
-
- /* SAT_UPDATE:
- * 0 - No Action
- * 1 - Update SAT with trigger
- * 2 - Update SAT without trigger
- */
- REG_UPDATE(DP_DPHY_SYM32_SAT_UPDATE,
- SAT_UPDATE, 1);
-
- /* wait for update to complete
- * (i.e. SAT_UPDATE_PENDING field is set to 0)
- * No need for HW to enforce keepout.
- */
- /* Best case and worst case wait time for SAT_UPDATE_PENDING
- * best: 109 us
- * worst: 868 us
- */
- REG_WAIT(DP_DPHY_SYM32_STATUS,
- SAT_UPDATE_PENDING, 0,
- 100, DP_SAT_UPDATE_MAX_RETRY);
-}
-
-void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(
- struct hpo_dp_link_encoder *enc,
- uint32_t stream_encoder_inst,
- struct fixed31_32 avg_time_slots_per_mtp)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- uint32_t x = dc_fixpt_floor(
- avg_time_slots_per_mtp);
- uint32_t y = dc_fixpt_ceil(
- dc_fixpt_shl(
- dc_fixpt_sub_int(
- avg_time_slots_per_mtp,
- x),
- 25));
-
- // If y rounds up to integer, carry it over to x.
- if (y >> 25) {
- x += 1;
- y = 0;
- }
-
- switch (stream_encoder_inst) {
- case 0:
- REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0,
- STREAM_VC_RATE_X, x,
- STREAM_VC_RATE_Y, y);
- break;
- case 1:
- REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, 0,
- STREAM_VC_RATE_X, x,
- STREAM_VC_RATE_Y, y);
- break;
- case 2:
- REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, 0,
- STREAM_VC_RATE_X, x,
- STREAM_VC_RATE_Y, y);
- break;
- case 3:
- REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL3, 0,
- STREAM_VC_RATE_X, x,
- STREAM_VC_RATE_Y, y);
- break;
- default:
- ASSERT(0);
- }
-
- /* Best case and worst case wait time for RATE_UPDATE_PENDING
- * best: 116 ns
- * worst: 903 ns
- */
- /* wait for update to be completed on the link */
- REG_WAIT(DP_DPHY_SYM32_STATUS,
- RATE_UPDATE_PENDING, 0,
- 1, 10);
-}
-
-static bool dcn31_hpo_dp_link_enc_is_in_alt_mode(
- struct hpo_dp_link_encoder *enc)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- uint32_t dp_alt_mode_disable = 0;
-
- ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
-
- /* if value == 1 alt mode is disabled, otherwise it is enabled */
- REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
- return (dp_alt_mode_disable == 0);
-}
-
-void dcn31_hpo_dp_link_enc_read_state(
- struct hpo_dp_link_encoder *enc,
- struct hpo_dp_link_enc_state *state)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
-
- ASSERT(state);
-
- REG_GET(DP_DPHY_SYM32_STATUS,
- STATUS, &state->link_enc_enabled);
- REG_GET(DP_DPHY_SYM32_CONTROL,
- NUM_LANES, &state->lane_count);
- REG_GET(DP_DPHY_SYM32_CONTROL,
- MODE, (uint32_t *)&state->link_mode);
-
- REG_GET_2(DP_DPHY_SYM32_SAT_VC0,
- SAT_STREAM_SOURCE, &state->stream_src[0],
- SAT_SLOT_COUNT, &state->slot_count[0]);
- REG_GET_2(DP_DPHY_SYM32_SAT_VC1,
- SAT_STREAM_SOURCE, &state->stream_src[1],
- SAT_SLOT_COUNT, &state->slot_count[1]);
- REG_GET_2(DP_DPHY_SYM32_SAT_VC2,
- SAT_STREAM_SOURCE, &state->stream_src[2],
- SAT_SLOT_COUNT, &state->slot_count[2]);
- REG_GET_2(DP_DPHY_SYM32_SAT_VC3,
- SAT_STREAM_SOURCE, &state->stream_src[3],
- SAT_SLOT_COUNT, &state->slot_count[3]);
-
- REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0,
- STREAM_VC_RATE_X, &state->vc_rate_x[0],
- STREAM_VC_RATE_Y, &state->vc_rate_y[0]);
- REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1,
- STREAM_VC_RATE_X, &state->vc_rate_x[1],
- STREAM_VC_RATE_Y, &state->vc_rate_y[1]);
- REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2,
- STREAM_VC_RATE_X, &state->vc_rate_x[2],
- STREAM_VC_RATE_Y, &state->vc_rate_y[2]);
- REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL3,
- STREAM_VC_RATE_X, &state->vc_rate_x[3],
- STREAM_VC_RATE_Y, &state->vc_rate_y[3]);
-}
-
-static enum bp_result link_transmitter_control(
- struct dcn31_hpo_dp_link_encoder *enc3,
- struct bp_transmitter_control *cntl)
-{
- enum bp_result result;
- struct dc_bios *bp = enc3->base.ctx->dc_bios;
-
- result = bp->funcs->transmitter_control(bp, cntl);
-
- return result;
-}
-
-/* enables DP PHY output for 128b132b encoding */
-void dcn31_hpo_dp_link_enc_enable_dp_output(
- struct hpo_dp_link_encoder *enc,
- const struct dc_link_settings *link_settings,
- enum transmitter transmitter,
- enum hpd_source_id hpd_source)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* Set the transmitter */
- enc3->base.transmitter = transmitter;
-
- /* Set the hpd source */
- enc3->base.hpd_source = hpd_source;
-
- /* Enable the PHY */
- cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = ENGINE_ID_UNKNOWN;
- cntl.transmitter = enc3->base.transmitter;
- //cntl.pll_id = clock_source;
- cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
- cntl.lanes_number = link_settings->lane_count;
- cntl.hpd_sel = enc3->base.hpd_source;
- cntl.pixel_clock = link_settings->link_rate * 1000;
- cntl.color_depth = COLOR_DEPTH_UNDEFINED;
- cntl.hpo_engine_id = enc->inst + ENGINE_ID_HPO_DP_0;
-
- result = link_transmitter_control(enc3, &cntl);
-
- if (result != BP_RESULT_OK) {
- DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- }
-}
-
-void dcn31_hpo_dp_link_enc_disable_output(
- struct hpo_dp_link_encoder *enc,
- enum signal_type signal)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* disable transmitter */
- cntl.action = TRANSMITTER_CONTROL_DISABLE;
- cntl.transmitter = enc3->base.transmitter;
- cntl.hpd_sel = enc3->base.hpd_source;
- cntl.signal = signal;
-
- result = link_transmitter_control(enc3, &cntl);
-
- if (result != BP_RESULT_OK) {
- DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- return;
- }
-
- /* disable encoder */
- dcn31_hpo_dp_link_enc_disable(enc);
-}
-
-void dcn31_hpo_dp_link_enc_set_ffe(
- struct hpo_dp_link_encoder *enc,
- const struct dc_link_settings *link_settings,
- uint8_t ffe_preset)
-{
- struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* disable transmitter */
- cntl.transmitter = enc3->base.transmitter;
- cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
- cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
- cntl.lanes_number = link_settings->lane_count;
- cntl.pixel_clock = link_settings->link_rate * 1000;
- cntl.lane_settings = ffe_preset;
-
- result = link_transmitter_control(enc3, &cntl);
-
- if (result != BP_RESULT_OK) {
- DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- return;
- }
-}
-
-static struct hpo_dp_link_encoder_funcs dcn31_hpo_dp_link_encoder_funcs = {
- .enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output,
- .disable_link_phy = dcn31_hpo_dp_link_enc_disable_output,
- .link_enable = dcn31_hpo_dp_link_enc_enable,
- .link_disable = dcn31_hpo_dp_link_enc_disable,
- .set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern,
- .update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table,
- .set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size,
- .is_in_alt_mode = dcn31_hpo_dp_link_enc_is_in_alt_mode,
- .read_state = dcn31_hpo_dp_link_enc_read_state,
- .set_ffe = dcn31_hpo_dp_link_enc_set_ffe,
-};
-
-void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
- const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
- const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask)
-{
- enc31->base.ctx = ctx;
-
- enc31->base.inst = inst;
- enc31->base.funcs = &dcn31_hpo_dp_link_encoder_funcs;
- enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN;
- enc31->base.transmitter = TRANSMITTER_UNKNOWN;
-
- enc31->regs = hpo_le_regs;
- enc31->hpo_le_shift = hpo_le_shift;
- enc31->hpo_le_mask = hpo_le_mask;
-}
+++ /dev/null
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DCN31_HPO_DP_LINK_ENCODER_H__
-#define __DAL_DCN31_HPO_DP_LINK_ENCODER_H__
-
-#include "link_encoder.h"
-
-
-#define DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(hpo_dp_link_encoder)\
- container_of(hpo_dp_link_encoder, struct dcn31_hpo_dp_link_encoder, base)
-
-
-#define DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id) \
- SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
- SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
- SRI(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
-
-#define DCN3_1_RDPCSTX_REG_LIST(id) \
- SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
-
-
-#define DCN3_1_HPO_DP_LINK_ENC_REGS \
- uint32_t DP_LINK_ENC_CLOCK_CONTROL;\
- uint32_t DP_DPHY_SYM32_CONTROL;\
- uint32_t DP_DPHY_SYM32_STATUS;\
- uint32_t DP_DPHY_SYM32_TP_CONFIG;\
- uint32_t DP_DPHY_SYM32_TP_PRBS_SEED0;\
- uint32_t DP_DPHY_SYM32_TP_PRBS_SEED1;\
- uint32_t DP_DPHY_SYM32_TP_PRBS_SEED2;\
- uint32_t DP_DPHY_SYM32_TP_PRBS_SEED3;\
- uint32_t DP_DPHY_SYM32_TP_SQ_PULSE;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM0;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM1;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM2;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM3;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM4;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM5;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM6;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM7;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM8;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM9;\
- uint32_t DP_DPHY_SYM32_TP_CUSTOM10;\
- uint32_t DP_DPHY_SYM32_SAT_VC0;\
- uint32_t DP_DPHY_SYM32_SAT_VC1;\
- uint32_t DP_DPHY_SYM32_SAT_VC2;\
- uint32_t DP_DPHY_SYM32_SAT_VC3;\
- uint32_t DP_DPHY_SYM32_VC_RATE_CNTL0;\
- uint32_t DP_DPHY_SYM32_VC_RATE_CNTL1;\
- uint32_t DP_DPHY_SYM32_VC_RATE_CNTL2;\
- uint32_t DP_DPHY_SYM32_VC_RATE_CNTL3;\
- uint32_t DP_DPHY_SYM32_SAT_UPDATE
-
-struct dcn31_hpo_dp_link_encoder_registers {
- DCN3_1_HPO_DP_LINK_ENC_REGS;
- uint32_t RDPCSTX_PHY_CNTL6[5];
-};
-
-#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
- SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
-
-#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
- SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
- SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
-
-#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
- DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
- DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
-
-#define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
- type DP_LINK_ENC_CLOCK_EN;\
- type DPHY_RESET;\
- type DPHY_ENABLE;\
- type PRECODER_ENABLE;\
- type NUM_LANES;\
- type MODE;\
- type STATUS;\
- type SAT_UPDATE_PENDING;\
- type RATE_UPDATE_PENDING;\
- type TP_CUSTOM;\
- type TP_SELECT0;\
- type TP_SELECT1;\
- type TP_SELECT2;\
- type TP_SELECT3;\
- type TP_PRBS_SEL0;\
- type TP_PRBS_SEL1;\
- type TP_PRBS_SEL2;\
- type TP_PRBS_SEL3;\
- type TP_SQ_PULSE_WIDTH;\
- type SAT_STREAM_SOURCE;\
- type SAT_SLOT_COUNT;\
- type STREAM_VC_RATE_X;\
- type STREAM_VC_RATE_Y;\
- type SAT_UPDATE;\
- type RDPCS_PHY_DPALT_DISABLE
-
-
-struct dcn31_hpo_dp_link_encoder_shift {
- DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint8_t);
-};
-
-struct dcn31_hpo_dp_link_encoder_mask {
- DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint32_t);
-};
-
-struct dcn31_hpo_dp_link_encoder {
- struct hpo_dp_link_encoder base;
- const struct dcn31_hpo_dp_link_encoder_registers *regs;
- const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift;
- const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask;
-};
-
-void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31,
- struct dc_context *ctx,
- uint32_t inst,
- const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
- const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
- const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);
-
-void dcn31_hpo_dp_link_enc_enable_dp_output(
- struct hpo_dp_link_encoder *enc,
- const struct dc_link_settings *link_settings,
- enum transmitter transmitter,
- enum hpd_source_id hpd_source);
-
-void dcn31_hpo_dp_link_enc_disable_output(
- struct hpo_dp_link_encoder *enc,
- enum signal_type signal);
-
-void dcn31_hpo_dp_link_enc_enable(
- struct hpo_dp_link_encoder *enc,
- enum dc_lane_count num_lanes);
-
-void dcn31_hpo_dp_link_enc_disable(
- struct hpo_dp_link_encoder *enc);
-
-void dcn31_hpo_dp_link_enc_set_link_test_pattern(
- struct hpo_dp_link_encoder *enc,
- struct encoder_set_dp_phy_pattern_param *tp_params);
-
-void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
- struct hpo_dp_link_encoder *enc,
- const struct link_mst_stream_allocation_table *table);
-
-void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(
- struct hpo_dp_link_encoder *enc,
- uint32_t stream_encoder_inst,
- struct fixed31_32 avg_time_slots_per_mtp);
-
-void dcn31_hpo_dp_link_enc_read_state(
- struct hpo_dp_link_encoder *enc,
- struct hpo_dp_link_enc_state *state);
-
-void dcn31_hpo_dp_link_enc_set_ffe(
- struct hpo_dp_link_encoder *enc,
- const struct dc_link_settings *link_settings,
- uint8_t ffe_preset);
-
-#endif // __DAL_DCN31_HPO_LINK_ENCODER_H__
+++ /dev/null
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dc_bios_types.h"
-#include "dcn31_hpo_dp_stream_encoder.h"
-#include "reg_helper.h"
-#include "dc.h"
-
-#define DC_LOGGER \
- enc3->base.ctx->logger
-
-#define REG(reg)\
- (enc3->regs->reg)
-
-#undef FN
-#define FN(reg_name, field_name) \
- enc3->hpo_se_shift->field_name, enc3->hpo_se_mask->field_name
-
-#define CTX \
- enc3->base.ctx
-
-
-enum dp2_pixel_encoding {
- DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444,
- DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422,
- DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420,
- DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY
-};
-
-enum dp2_uncompressed_component_depth {
- DP_SYM32_ENC_COMPONENT_DEPTH_6BPC,
- DP_SYM32_ENC_COMPONENT_DEPTH_8BPC,
- DP_SYM32_ENC_COMPONENT_DEPTH_10BPC,
- DP_SYM32_ENC_COMPONENT_DEPTH_12BPC
-};
-
-
-static void dcn31_hpo_dp_stream_enc_enable_stream(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Enable all clocks in the DP_STREAM_ENC */
- REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,
- DP_STREAM_ENC_CLOCK_EN, 1);
-
- /* Assert reset to the DP_SYM32_ENC logic */
- REG_UPDATE(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_RESET, 1);
- /* Wait for reset to complete (to assert) */
- REG_WAIT(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_RESET_DONE, 1,
- 1, 10);
-
- /* De-assert reset to the DP_SYM32_ENC logic */
- REG_UPDATE(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_RESET, 0);
- /* Wait for reset to de-assert */
- REG_WAIT(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_RESET_DONE, 0,
- 1, 10);
-
- /* Enable idle pattern generation */
- REG_UPDATE(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_ENABLE, 1);
-}
-
-static void dcn31_hpo_dp_stream_enc_dp_unblank(
- struct hpo_dp_stream_encoder *enc,
- uint32_t stream_source)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Set the input mux for video stream source */
- REG_UPDATE(DP_STREAM_ENC_INPUT_MUX_CONTROL,
- DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, stream_source);
-
- /* Enable video transmission in main framer */
- REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,
- VID_STREAM_ENABLE, 1);
-
- /* Reset and Enable Pixel to Symbol FIFO */
- REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
- PIXEL_TO_SYMBOL_FIFO_RESET, 1);
- REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL,
- PIXEL_TO_SYMBOL_FIFO_RESET_DONE, 1,
- 1, 10);
- REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
- PIXEL_TO_SYMBOL_FIFO_RESET, 0);
- REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */
- PIXEL_TO_SYMBOL_FIFO_RESET_DONE, 0,
- 1, 10);
- REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
- PIXEL_TO_SYMBOL_FIFO_ENABLE, 1);
-
- /* Reset and Enable Clock Ramp Adjuster FIFO */
- REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_RESET, 1);
- REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_RESET_DONE, 1,
- 1, 10);
- REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_RESET, 0);
- REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_RESET_DONE, 0,
- 1, 10);
-
- /* For Debug -- Enable CRC */
- REG_UPDATE_2(DP_SYM32_ENC_VID_CRC_CONTROL,
- CRC_ENABLE, 1,
- CRC_CONT_MODE_ENABLE, 1);
-
- REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_ENABLE, 1);
-}
-
-static void dcn31_hpo_dp_stream_enc_dp_blank(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Disable video transmission */
- REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,
- VID_STREAM_ENABLE, 0);
-
- /* Wait for video stream transmission disabled
- * Larger delay to wait until VBLANK - use max retry of
- * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
- * a little more because we may not trust delay accuracy.
- */
- REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL,
- VID_STREAM_STATUS, 0,
- 10, 5000);
-
- /* Disable SDP transmission */
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 0);
-
- /* Disable Pixel to Symbol FIFO */
- REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
- PIXEL_TO_SYMBOL_FIFO_ENABLE, 0);
-
- /* Disable Clock Ramp Adjuster FIFO */
- REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
- FIFO_ENABLE, 0);
-}
-
-static void dcn31_hpo_dp_stream_enc_disable(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Disable DP_SYM32_ENC */
- REG_UPDATE(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_ENABLE, 0);
-
- /* Disable clocks in the DP_STREAM_ENC */
- REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,
- DP_STREAM_ENC_CLOCK_EN, 0);
-}
-
-static void dcn31_hpo_dp_stream_enc_set_stream_attribute(
- struct hpo_dp_stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing,
- enum dc_color_space output_color_space,
- bool use_vsc_sdp_for_colorimetry,
- bool compressed_format,
- bool double_buffer_en)
-{
- enum dp2_pixel_encoding pixel_encoding;
- enum dp2_uncompressed_component_depth component_depth;
- uint32_t h_active_start;
- uint32_t v_active_start;
- uint32_t h_blank;
- uint32_t h_back_porch;
- uint32_t h_width;
- uint32_t v_height;
- uint64_t v_freq;
- uint8_t misc0 = 0;
- uint8_t misc1 = 0;
- uint8_t hsp;
- uint8_t vsp;
-
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
- struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
-
- /* MISC0[0] = 0 video and link clocks are asynchronous
- * MISC1[0] = 0 interlace not supported
- * MISC1[2:1] = 0 stereo field is handled by hardware
- * MISC1[5:3] = 0 Reserved
- */
-
- /* Interlaced not supported */
- if (hw_crtc_timing.flags.INTERLACE) {
- BREAK_TO_DEBUGGER();
- }
-
- /* Double buffer enable for MSA and pixel format registers
- * Only double buffer for changing stream attributes for active streams
- * Do not double buffer when initially enabling a stream
- */
- REG_UPDATE(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL,
- MSA_DOUBLE_BUFFER_ENABLE, double_buffer_en);
- REG_UPDATE(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL,
- PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, double_buffer_en);
-
- /* Pixel Encoding */
- switch (hw_crtc_timing.pixel_encoding) {
- case PIXEL_ENCODING_YCBCR422:
- pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422;
- misc0 = misc0 | 0x2; // MISC0[2:1] = 01
- break;
- case PIXEL_ENCODING_YCBCR444:
- pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444;
- misc0 = misc0 | 0x4; // MISC0[2:1] = 10
-
- if (hw_crtc_timing.flags.Y_ONLY) {
- pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY;
- if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) {
- /* HW testing only, no use case yet.
- * Color depth of Y-only could be
- * 8, 10, 12, 16 bits
- */
- misc1 = misc1 | 0x80; // MISC1[7] = 1
- }
- }
- break;
- case PIXEL_ENCODING_YCBCR420:
- pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420;
- misc1 = misc1 | 0x40; // MISC1[6] = 1
- break;
- case PIXEL_ENCODING_RGB:
- default:
- pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444;
- break;
- }
-
- /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
- * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
- * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
- * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
- */
- if (use_vsc_sdp_for_colorimetry)
- misc1 = misc1 | 0x40;
- else
- misc1 = misc1 & ~0x40;
-
- /* Color depth */
- switch (hw_crtc_timing.display_color_depth) {
- case COLOR_DEPTH_666:
- component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
- // MISC0[7:5] = 000
- break;
- case COLOR_DEPTH_888:
- component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_8BPC;
- misc0 = misc0 | 0x20; // MISC0[7:5] = 001
- break;
- case COLOR_DEPTH_101010:
- component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_10BPC;
- misc0 = misc0 | 0x40; // MISC0[7:5] = 010
- break;
- case COLOR_DEPTH_121212:
- component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_12BPC;
- misc0 = misc0 | 0x60; // MISC0[7:5] = 011
- break;
- default:
- component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
- break;
- }
-
- REG_UPDATE_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,
- PIXEL_ENCODING_TYPE, compressed_format,
- UNCOMPRESSED_PIXEL_ENCODING, pixel_encoding,
- UNCOMPRESSED_COMPONENT_DEPTH, component_depth);
-
- switch (output_color_space) {
- case COLOR_SPACE_SRGB:
- misc1 = misc1 & ~0x80; /* bit7 = 0*/
- break;
- case COLOR_SPACE_SRGB_LIMITED:
- misc0 = misc0 | 0x8; /* bit3=1 */
- misc1 = misc1 & ~0x80; /* bit7 = 0*/
- break;
- case COLOR_SPACE_YCBCR601:
- case COLOR_SPACE_YCBCR601_LIMITED:
- misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
- misc1 = misc1 & ~0x80; /* bit7 = 0*/
- if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
- misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
- else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
- misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
- break;
- case COLOR_SPACE_YCBCR709:
- case COLOR_SPACE_YCBCR709_LIMITED:
- misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
- misc1 = misc1 & ~0x80; /* bit7 = 0*/
- if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
- misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
- else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
- misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
- break;
- case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
- case COLOR_SPACE_2020_RGB_FULLRANGE:
- case COLOR_SPACE_2020_YCBCR:
- case COLOR_SPACE_XR_RGB:
- case COLOR_SPACE_MSREF_SCRGB:
- case COLOR_SPACE_ADOBERGB:
- case COLOR_SPACE_DCIP3:
- case COLOR_SPACE_XV_YCC_709:
- case COLOR_SPACE_XV_YCC_601:
- case COLOR_SPACE_DISPLAYNATIVE:
- case COLOR_SPACE_DOLBYVISION:
- case COLOR_SPACE_APPCTRL:
- case COLOR_SPACE_CUSTOMPOINTS:
- case COLOR_SPACE_UNKNOWN:
- case COLOR_SPACE_YCBCR709_BLACK:
- /* do nothing */
- break;
- }
-
- /* calculate from vesa timing parameters
- * h_active_start related to leading edge of sync
- */
- h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
- hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
-
- h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
- hw_crtc_timing.h_sync_width;
-
- /* start at beginning of left border */
- h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
-
- v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
- hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
- hw_crtc_timing.v_front_porch;
-
- h_width = hw_crtc_timing.h_border_left + hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right;
- v_height = hw_crtc_timing.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom;
- hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0 : 0x80;
- vsp = hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 0 : 0x80;
- v_freq = (uint64_t)hw_crtc_timing.pix_clk_100hz * 100;
-
- /* MSA Packet Mapping to 32-bit Link Symbols - DP2 spec, section 2.7.4.1
- *
- * Lane 0 Lane 1 Lane 2 Lane 3
- * MSA[0] = { 0, 0, 0, VFREQ[47:40]}
- * MSA[1] = { 0, 0, 0, VFREQ[39:32]}
- * MSA[2] = { 0, 0, 0, VFREQ[31:24]}
- * MSA[3] = { HTotal[15:8], HStart[15:8], HWidth[15:8], VFREQ[23:16]}
- * MSA[4] = { HTotal[ 7:0], HStart[ 7:0], HWidth[ 7:0], VFREQ[15: 8]}
- * MSA[5] = { VTotal[15:8], VStart[15:8], VHeight[15:8], VFREQ[ 7: 0]}
- * MSA[6] = { VTotal[ 7:0], VStart[ 7:0], VHeight[ 7:0], MISC0[ 7: 0]}
- * MSA[7] = { HSP|HSW[14:8], VSP|VSW[14:8], 0, MISC1[ 7: 0]}
- * MSA[8] = { HSW[ 7:0], VSW[ 7:0], 0, 0}
- */
- REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0,
- MSA_DATA_LANE_0, 0,
- MSA_DATA_LANE_1, 0,
- MSA_DATA_LANE_2, 0,
- MSA_DATA_LANE_3, v_freq >> 40);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0,
- MSA_DATA_LANE_0, 0,
- MSA_DATA_LANE_1, 0,
- MSA_DATA_LANE_2, 0,
- MSA_DATA_LANE_3, (v_freq >> 32) & 0xff);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0,
- MSA_DATA_LANE_0, 0,
- MSA_DATA_LANE_1, 0,
- MSA_DATA_LANE_2, 0,
- MSA_DATA_LANE_3, (v_freq >> 24) & 0xff);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0,
- MSA_DATA_LANE_0, hw_crtc_timing.h_total >> 8,
- MSA_DATA_LANE_1, h_active_start >> 8,
- MSA_DATA_LANE_2, h_width >> 8,
- MSA_DATA_LANE_3, (v_freq >> 16) & 0xff);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0,
- MSA_DATA_LANE_0, hw_crtc_timing.h_total & 0xff,
- MSA_DATA_LANE_1, h_active_start & 0xff,
- MSA_DATA_LANE_2, h_width & 0xff,
- MSA_DATA_LANE_3, (v_freq >> 8) & 0xff);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0,
- MSA_DATA_LANE_0, hw_crtc_timing.v_total >> 8,
- MSA_DATA_LANE_1, v_active_start >> 8,
- MSA_DATA_LANE_2, v_height >> 8,
- MSA_DATA_LANE_3, v_freq & 0xff);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0,
- MSA_DATA_LANE_0, hw_crtc_timing.v_total & 0xff,
- MSA_DATA_LANE_1, v_active_start & 0xff,
- MSA_DATA_LANE_2, v_height & 0xff,
- MSA_DATA_LANE_3, misc0);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0,
- MSA_DATA_LANE_0, hsp | (hw_crtc_timing.h_sync_width >> 8),
- MSA_DATA_LANE_1, vsp | (hw_crtc_timing.v_sync_width >> 8),
- MSA_DATA_LANE_2, 0,
- MSA_DATA_LANE_3, misc1);
-
- REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0,
- MSA_DATA_LANE_0, hw_crtc_timing.h_sync_width & 0xff,
- MSA_DATA_LANE_1, hw_crtc_timing.v_sync_width & 0xff,
- MSA_DATA_LANE_2, 0,
- MSA_DATA_LANE_3, 0);
-}
-
-static void dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(
- struct hpo_dp_stream_encoder *enc,
- struct encoder_info_frame *info_frame)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- if (info_frame->adaptive_sync.valid == true &&
- info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {
- //00: REFER_TO_DP_SOF, 01: REFER_TO_OTG_SOF
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, 1);
-
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER,
- info_frame->sdp_line_num.adaptive_sync_line_num);
- }
-}
-
-static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(
- struct hpo_dp_stream_encoder *enc,
- const struct encoder_info_frame *info_frame)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
- uint32_t dmdata_packet_enabled = 0;
-
- if (info_frame->vsc.valid)
- enc->vpg->funcs->update_generic_info_packet(
- enc->vpg,
- 0, /* packetIndex */
- &info_frame->vsc,
- true);
-
- if (info_frame->spd.valid)
- enc->vpg->funcs->update_generic_info_packet(
- enc->vpg,
- 2, /* packetIndex */
- &info_frame->spd,
- true);
-
- if (info_frame->hdrsmd.valid)
- enc->vpg->funcs->update_generic_info_packet(
- enc->vpg,
- 3, /* packetIndex */
- &info_frame->hdrsmd,
- true);
-
- /* packetIndex 4 is used for send immediate sdp message, and please
- * use other packetIndex (such as 5,6) for other info packet
- */
-
- if (info_frame->adaptive_sync.valid)
- enc->vpg->funcs->update_generic_info_packet(
- enc->vpg,
- 5, /* packetIndex */
- &info_frame->adaptive_sync,
- true);
-
- /* enable/disable transmission of packet(s).
- * If enabled, packet transmission begins on the next frame
- */
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->vsc.valid);
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->spd.valid);
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->hdrsmd.valid);
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->adaptive_sync.valid);
-
- /* check if dynamic metadata packet transmission is enabled */
- REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL,
- METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
-
- /* Enable secondary data path */
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 1);
-}
-
-static void dcn31_hpo_dp_stream_enc_stop_dp_info_packets(
- struct hpo_dp_stream_encoder *enc)
-{
- /* stop generic packets on DP */
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
- uint32_t asp_enable = 0;
- uint32_t atp_enable = 0;
- uint32_t aip_enable = 0;
- uint32_t acm_enable = 0;
-
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
-
- /* Disable secondary data path if audio is also disabled */
- REG_GET_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
- ASP_ENABLE, &asp_enable,
- ATP_ENABLE, &atp_enable,
- AIP_ENABLE, &aip_enable,
- ACM_ENABLE, &acm_enable);
- if (!(asp_enable || atp_enable || aip_enable || acm_enable))
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 0);
-}
-
-static uint32_t hpo_dp_is_gsp_enabled(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
- uint32_t gsp0_enabled = 0;
- uint32_t gsp2_enabled = 0;
- uint32_t gsp3_enabled = 0;
- uint32_t gsp11_enabled = 0;
-
- REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled);
- REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled);
- REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp3_enabled);
- REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL11, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp11_enabled);
-
- return (gsp0_enabled || gsp2_enabled || gsp3_enabled || gsp11_enabled);
-}
-
-static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet(
- struct hpo_dp_stream_encoder *enc,
- bool enable,
- uint8_t *dsc_packed_pps,
- bool immediate_update)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- if (enable) {
- struct dc_info_packet pps_sdp;
- int i;
-
- /* Configure for PPS packet size (128 bytes) */
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
- GSP_PAYLOAD_SIZE, 3);
-
- /* Load PPS into infoframe (SDP) registers */
- pps_sdp.valid = true;
- pps_sdp.hb0 = 0;
- pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
- pps_sdp.hb2 = 127;
- pps_sdp.hb3 = 0;
-
- for (i = 0; i < 4; i++) {
- memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
- enc3->base.vpg->funcs->update_generic_info_packet(
- enc3->base.vpg,
- 11 + i,
- &pps_sdp,
- immediate_update);
- }
-
- /* SW should make sure VBID[6] update line number is bigger
- * than PPS transmit line number
- */
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
- GSP_TRANSMISSION_LINE_NUMBER, 2);
-
- REG_UPDATE_2(DP_SYM32_ENC_VID_VBID_CONTROL,
- VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, 0,
- VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, 3);
-
- /* Send PPS data at the line number specified above. */
- REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
- GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 1);
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 1);
- } else {
- /* Disable Generic Stream Packet 11 (GSP) transmission */
- REG_UPDATE_2(DP_SYM32_ENC_SDP_GSP_CONTROL11,
- GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0,
- GSP_PAYLOAD_SIZE, 0);
- }
-}
-
-static void dcn31_hpo_dp_stream_enc_map_stream_to_link(
- struct hpo_dp_stream_encoder *enc,
- uint32_t stream_enc_inst,
- uint32_t link_enc_inst)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- ASSERT(stream_enc_inst < 4 && link_enc_inst < 2);
-
- switch (stream_enc_inst) {
- case 0:
- REG_UPDATE(DP_STREAM_MAPPER_CONTROL0,
- DP_STREAM_LINK_TARGET, link_enc_inst);
- break;
- case 1:
- REG_UPDATE(DP_STREAM_MAPPER_CONTROL1,
- DP_STREAM_LINK_TARGET, link_enc_inst);
- break;
- case 2:
- REG_UPDATE(DP_STREAM_MAPPER_CONTROL2,
- DP_STREAM_LINK_TARGET, link_enc_inst);
- break;
- case 3:
- REG_UPDATE(DP_STREAM_MAPPER_CONTROL3,
- DP_STREAM_LINK_TARGET, link_enc_inst);
- break;
- }
-}
-
-static void dcn31_hpo_dp_stream_enc_audio_setup(
- struct hpo_dp_stream_encoder *enc,
- unsigned int az_inst,
- struct audio_info *info)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Set the input mux for video stream source */
- REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL,
- DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst);
-
- ASSERT(enc->apg);
- enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info);
-}
-
-static void dcn31_hpo_dp_stream_enc_audio_enable(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Enable Audio packets */
- REG_UPDATE(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, 1);
-
- /* Program the ATP and AIP next */
- REG_UPDATE_2(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
- ATP_ENABLE, 1,
- AIP_ENABLE, 1);
-
- /* Enable secondary data path */
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 1);
-
- /* Enable APG block */
- enc->apg->funcs->enable_apg(enc->apg);
-}
-
-static void dcn31_hpo_dp_stream_enc_audio_disable(
- struct hpo_dp_stream_encoder *enc)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- /* Disable Audio packets */
- REG_UPDATE_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
- ASP_ENABLE, 0,
- ATP_ENABLE, 0,
- AIP_ENABLE, 0,
- ACM_ENABLE, 0);
-
- /* Disable STP Stream Enable if other SDP GSP are also disabled */
- if (!(hpo_dp_is_gsp_enabled(enc)))
- REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, 0);
-
- /* Disable APG block */
- enc->apg->funcs->disable_apg(enc->apg);
-}
-
-static void dcn31_hpo_dp_stream_enc_read_state(
- struct hpo_dp_stream_encoder *enc,
- struct hpo_dp_stream_encoder_state *s)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- REG_GET(DP_SYM32_ENC_CONTROL,
- DP_SYM32_ENC_ENABLE, &s->stream_enc_enabled);
- REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL,
- VID_STREAM_ENABLE, &s->vid_stream_enabled);
- REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL,
- DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, &s->otg_inst);
-
- REG_GET_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,
- PIXEL_ENCODING_TYPE, &s->compressed_format,
- UNCOMPRESSED_PIXEL_ENCODING, &s->pixel_encoding,
- UNCOMPRESSED_COMPONENT_DEPTH, &s->component_depth);
-
- REG_GET(DP_SYM32_ENC_SDP_CONTROL,
- SDP_STREAM_ENABLE, &s->sdp_enabled);
-
- switch (enc->inst) {
- case 0:
- REG_GET(DP_STREAM_MAPPER_CONTROL0,
- DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
- break;
- case 1:
- REG_GET(DP_STREAM_MAPPER_CONTROL1,
- DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
- break;
- case 2:
- REG_GET(DP_STREAM_MAPPER_CONTROL2,
- DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
- break;
- case 3:
- REG_GET(DP_STREAM_MAPPER_CONTROL3,
- DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
- break;
- }
-}
-
-static void dcn31_set_hblank_min_symbol_width(
- struct hpo_dp_stream_encoder *enc,
- uint16_t width)
-{
- struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
-
- REG_SET(DP_SYM32_ENC_HBLANK_CONTROL, 0,
- HBLANK_MINIMUM_SYMBOL_WIDTH, width);
-}
-
-static const struct hpo_dp_stream_encoder_funcs dcn30_str_enc_funcs = {
- .enable_stream = dcn31_hpo_dp_stream_enc_enable_stream,
- .dp_unblank = dcn31_hpo_dp_stream_enc_dp_unblank,
- .dp_blank = dcn31_hpo_dp_stream_enc_dp_blank,
- .disable = dcn31_hpo_dp_stream_enc_disable,
- .set_stream_attribute = dcn31_hpo_dp_stream_enc_set_stream_attribute,
- .update_dp_info_packets_sdp_line_num = dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num,
- .update_dp_info_packets = dcn31_hpo_dp_stream_enc_update_dp_info_packets,
- .stop_dp_info_packets = dcn31_hpo_dp_stream_enc_stop_dp_info_packets,
- .dp_set_dsc_pps_info_packet = dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet,
- .map_stream_to_link = dcn31_hpo_dp_stream_enc_map_stream_to_link,
- .dp_audio_setup = dcn31_hpo_dp_stream_enc_audio_setup,
- .dp_audio_enable = dcn31_hpo_dp_stream_enc_audio_enable,
- .dp_audio_disable = dcn31_hpo_dp_stream_enc_audio_disable,
- .read_state = dcn31_hpo_dp_stream_enc_read_state,
- .set_hblank_min_symbol_width = dcn31_set_hblank_min_symbol_width,
-};
-
-void dcn31_hpo_dp_stream_encoder_construct(
- struct dcn31_hpo_dp_stream_encoder *enc3,
- struct dc_context *ctx,
- struct dc_bios *bp,
- uint32_t inst,
- enum engine_id eng_id,
- struct vpg *vpg,
- struct apg *apg,
- const struct dcn31_hpo_dp_stream_encoder_registers *regs,
- const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
- const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask)
-{
- enc3->base.funcs = &dcn30_str_enc_funcs;
- enc3->base.ctx = ctx;
- enc3->base.inst = inst;
- enc3->base.id = eng_id;
- enc3->base.bp = bp;
- enc3->base.vpg = vpg;
- enc3->base.apg = apg;
- enc3->regs = regs;
- enc3->hpo_se_shift = hpo_se_shift;
- enc3->hpo_se_mask = hpo_se_mask;
-}
+++ /dev/null
-/*
- * Copyright 2019 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
-#define __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
-
-#include "dcn30/dcn30_vpg.h"
-#include "dcn31/dcn31_apg.h"
-#include "stream_encoder.h"
-
-
-#define DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_dp_stream_encoder)\
- container_of(hpo_dp_stream_encoder, struct dcn31_hpo_dp_stream_encoder, base)
-
-
-/* Define MSA_DATA_LANE_[0-3] fields to make programming easier */
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0__SHIFT 0x0
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1__SHIFT 0x8
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2__SHIFT 0x10
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3__SHIFT 0x18
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0_MASK 0x000000FFL
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1_MASK 0x0000FF00L
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2_MASK 0x00FF0000L
-#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3_MASK 0xFF000000L
-
-
-#define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id) \
- SR(DP_STREAM_MAPPER_CONTROL0),\
- SR(DP_STREAM_MAPPER_CONTROL1),\
- SR(DP_STREAM_MAPPER_CONTROL2),\
- SR(DP_STREAM_MAPPER_CONTROL3),\
- SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\
- SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\
- SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\
- SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\
- SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\
- SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
- SRI(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
-
-#define DCN3_1_HPO_DP_STREAM_ENC_REGS \
- uint32_t DP_STREAM_MAPPER_CONTROL0;\
- uint32_t DP_STREAM_MAPPER_CONTROL1;\
- uint32_t DP_STREAM_MAPPER_CONTROL2;\
- uint32_t DP_STREAM_MAPPER_CONTROL3;\
- uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\
- uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\
- uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\
- uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\
- uint32_t DP_SYM32_ENC_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\
- uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_MSA0;\
- uint32_t DP_SYM32_ENC_VID_MSA1;\
- uint32_t DP_SYM32_ENC_VID_MSA2;\
- uint32_t DP_SYM32_ENC_VID_MSA3;\
- uint32_t DP_SYM32_ENC_VID_MSA4;\
- uint32_t DP_SYM32_ENC_VID_MSA5;\
- uint32_t DP_SYM32_ENC_VID_MSA6;\
- uint32_t DP_SYM32_ENC_VID_MSA7;\
- uint32_t DP_SYM32_ENC_VID_MSA8;\
- uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\
- uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\
- uint32_t DP_SYM32_ENC_SDP_CONTROL;\
- uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\
- uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\
- uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\
- uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\
- uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\
- uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\
- uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\
- uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\
- uint32_t DP_SYM32_ENC_HBLANK_CONTROL
-
-
-#define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
- SE_SF(DP_STREAM_MAPPER_CONTROL0, DP_STREAM_LINK_TARGET, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC_CLOCK_EN, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE, mask_sh),\
- SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET_DONE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_ENCODING, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, MSA_DOUBLE_BUFFER_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_0, mask_sh),\
- SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_1, mask_sh),\
- SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_2, mask_sh),\
- SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_3, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET_DONE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_STATUS, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL, SDP_STREAM_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_PAYLOAD_SIZE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, METADATA_PACKET_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AUDIO_MUTE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ATP_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh),\
- SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
-
-
-#define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
- type DP_STREAM_LINK_TARGET;\
- type DP_STREAM_ENC_CLOCK_EN;\
- type DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL;\
- type DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
- type FIFO_RESET;\
- type FIFO_RESET_DONE;\
- type FIFO_ENABLE;\
- type DP_SYM32_ENC_RESET;\
- type DP_SYM32_ENC_RESET_DONE;\
- type DP_SYM32_ENC_ENABLE;\
- type PIXEL_ENCODING_TYPE;\
- type UNCOMPRESSED_PIXEL_ENCODING;\
- type UNCOMPRESSED_COMPONENT_DEPTH;\
- type PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE;\
- type MSA_DOUBLE_BUFFER_ENABLE;\
- type MSA_DATA_LANE_0;\
- type MSA_DATA_LANE_1;\
- type MSA_DATA_LANE_2;\
- type MSA_DATA_LANE_3;\
- type PIXEL_TO_SYMBOL_FIFO_RESET;\
- type PIXEL_TO_SYMBOL_FIFO_RESET_DONE;\
- type PIXEL_TO_SYMBOL_FIFO_ENABLE;\
- type VID_STREAM_ENABLE;\
- type VID_STREAM_STATUS;\
- type VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE;\
- type VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER;\
- type SDP_STREAM_ENABLE;\
- type AUDIO_MUTE;\
- type ASP_ENABLE;\
- type ATP_ENABLE;\
- type AIP_ENABLE;\
- type ACM_ENABLE;\
- type GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE;\
- type GSP_PAYLOAD_SIZE;\
- type GSP_TRANSMISSION_LINE_NUMBER;\
- type GSP_SOF_REFERENCE;\
- type METADATA_PACKET_ENABLE;\
- type CRC_ENABLE;\
- type CRC_CONT_MODE_ENABLE;\
- type HBLANK_MINIMUM_SYMBOL_WIDTH
-
-
-struct dcn31_hpo_dp_stream_encoder_registers {
- DCN3_1_HPO_DP_STREAM_ENC_REGS;
-};
-
-struct dcn31_hpo_dp_stream_encoder_shift {
- DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
-};
-
-struct dcn31_hpo_dp_stream_encoder_mask {
- DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
-};
-
-struct dcn31_hpo_dp_stream_encoder {
- struct hpo_dp_stream_encoder base;
- const struct dcn31_hpo_dp_stream_encoder_registers *regs;
- const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift;
- const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask;
-};
-
-
-void dcn31_hpo_dp_stream_encoder_construct(
- struct dcn31_hpo_dp_stream_encoder *enc3,
- struct dc_context *ctx,
- struct dc_bios *bp,
- uint32_t inst,
- enum engine_id eng_id,
- struct vpg *vpg,
- struct apg *apg,
- const struct dcn31_hpo_dp_stream_encoder_registers *regs,
- const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
- const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
-
-
-#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
ifdef CONFIG_DRM_AMD_DC_FP
###############################################################################
+# DCN30
+###############################################################################
+
+AMD_DAL_HPO_DCN30 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn30/,$(HPO_DCN30))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN30)
+###############################################################################
+# DCN31
+###############################################################################
+HPO_DCN31 = dcn31_hpo_dp_stream_encoder.o dcn31_hpo_dp_link_encoder.o
+
+AMD_DAL_HPO_DCN31 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn31/,$(HPO_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN31)
+###############################################################################
# DCN32
###############################################################################
HPO_DCN32 = dcn32_hpo_dp_link_encoder.o
--- /dev/null
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc_bios_types.h"
+#include "dcn31_hpo_dp_link_encoder.h"
+#include "reg_helper.h"
+#include "stream_encoder.h"
+
+#define DC_LOGGER \
+ enc3->base.ctx->logger
+
+#define REG(reg)\
+ (enc3->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name
+
+
+#define CTX \
+ enc3->base.ctx
+
+enum {
+ DP_SAT_UPDATE_MAX_RETRY = 200
+};
+
+void dcn31_hpo_dp_link_enc_enable(
+ struct hpo_dp_link_encoder *enc,
+ enum dc_lane_count num_lanes)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ uint32_t dp_link_enabled;
+
+ /* get current status of link enabled */
+ REG_GET(DP_DPHY_SYM32_STATUS,
+ STATUS, &dp_link_enabled);
+
+ /* Enable clocks first */
+ REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 1);
+
+ /* Reset DPHY. Only reset if going from disable to enable */
+ if (!dp_link_enabled) {
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 1);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 0);
+ }
+
+ /* Configure DPHY settings */
+ REG_UPDATE_3(DP_DPHY_SYM32_CONTROL,
+ DPHY_ENABLE, 1,
+ PRECODER_ENABLE, 1,
+ NUM_LANES, num_lanes == LANE_COUNT_ONE ? 0 : num_lanes == LANE_COUNT_TWO ? 1 : 3);
+}
+
+void dcn31_hpo_dp_link_enc_disable(
+ struct hpo_dp_link_encoder *enc)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+
+ /* Configure DPHY settings */
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ DPHY_ENABLE, 0);
+
+ /* Shut down clock last */
+ REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 0);
+}
+
+void dcn31_hpo_dp_link_enc_set_link_test_pattern(
+ struct hpo_dp_link_encoder *enc,
+ struct encoder_set_dp_phy_pattern_param *tp_params)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ uint32_t tp_custom;
+
+ switch (tp_params->dp_phy_pattern) {
+ case DP_TEST_PATTERN_VIDEO_MODE:
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_LINK_ACTIVE);
+ break;
+ case DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE:
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_LINK_TRAINING_TPS1);
+ break;
+ case DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE:
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_LINK_TRAINING_TPS2);
+ break;
+ case DP_TEST_PATTERN_128b_132b_TPS1:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_TPS1,
+ TP_SELECT1, DP_DPHY_TP_SELECT_TPS1,
+ TP_SELECT2, DP_DPHY_TP_SELECT_TPS1,
+ TP_SELECT3, DP_DPHY_TP_SELECT_TPS1);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_128b_132b_TPS2:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_TPS2,
+ TP_SELECT1, DP_DPHY_TP_SELECT_TPS2,
+ TP_SELECT2, DP_DPHY_TP_SELECT_TPS2,
+ TP_SELECT3, DP_DPHY_TP_SELECT_TPS2);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS7:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS7,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS7,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS7,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS7);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS9:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS9,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS9,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS9,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS9);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS11:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS11,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS11,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS11,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS11);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS15:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS15,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS15,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS15,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS15);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS23:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS23,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS23,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS23,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS23);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_PRBS31:
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_PRBS_SEL0, DP_DPHY_TP_PRBS31,
+ TP_PRBS_SEL1, DP_DPHY_TP_PRBS31,
+ TP_PRBS_SEL2, DP_DPHY_TP_PRBS31,
+ TP_PRBS_SEL3, DP_DPHY_TP_PRBS31);
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT1, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT2, DP_DPHY_TP_SELECT_PRBS,
+ TP_SELECT3, DP_DPHY_TP_SELECT_PRBS);
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_264BIT_CUSTOM:
+ tp_custom = (tp_params->custom_pattern[2] << 16) | (tp_params->custom_pattern[1] << 8) | tp_params->custom_pattern[0];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[5] << 16) | (tp_params->custom_pattern[4] << 8) | tp_params->custom_pattern[3];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[8] << 16) | (tp_params->custom_pattern[7] << 8) | tp_params->custom_pattern[6];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[11] << 16) | (tp_params->custom_pattern[10] << 8) | tp_params->custom_pattern[9];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[14] << 16) | (tp_params->custom_pattern[13] << 8) | tp_params->custom_pattern[12];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[17] << 16) | (tp_params->custom_pattern[16] << 8) | tp_params->custom_pattern[15];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[20] << 16) | (tp_params->custom_pattern[19] << 8) | tp_params->custom_pattern[18];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[23] << 16) | (tp_params->custom_pattern[22] << 8) | tp_params->custom_pattern[21];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[26] << 16) | (tp_params->custom_pattern[25] << 8) | tp_params->custom_pattern[24];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[29] << 16) | (tp_params->custom_pattern[28] << 8) | tp_params->custom_pattern[27];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM9, 0, TP_CUSTOM, tp_custom);
+ tp_custom = (tp_params->custom_pattern[32] << 16) | (tp_params->custom_pattern[31] << 8) | tp_params->custom_pattern[30];
+ REG_SET(DP_DPHY_SYM32_TP_CUSTOM10, 0, TP_CUSTOM, tp_custom);
+
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_CUSTOM,
+ TP_SELECT1, DP_DPHY_TP_SELECT_CUSTOM,
+ TP_SELECT2, DP_DPHY_TP_SELECT_CUSTOM,
+ TP_SELECT3, DP_DPHY_TP_SELECT_CUSTOM);
+
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ case DP_TEST_PATTERN_SQUARE:
+ case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:
+ case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:
+ case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:
+ REG_SET(DP_DPHY_SYM32_TP_SQ_PULSE, 0,
+ TP_SQ_PULSE_WIDTH, tp_params->custom_pattern[0]);
+
+ REG_UPDATE_4(DP_DPHY_SYM32_TP_CONFIG,
+ TP_SELECT0, DP_DPHY_TP_SELECT_SQUARE,
+ TP_SELECT1, DP_DPHY_TP_SELECT_SQUARE,
+ TP_SELECT2, DP_DPHY_TP_SELECT_SQUARE,
+ TP_SELECT3, DP_DPHY_TP_SELECT_SQUARE);
+
+ REG_UPDATE(DP_DPHY_SYM32_CONTROL,
+ MODE, DP2_TEST_PATTERN);
+ break;
+ default:
+ break;
+ }
+}
+
+static void fill_stream_allocation_row_info(
+ const struct link_mst_stream_allocation *stream_allocation,
+ uint32_t *src,
+ uint32_t *slots)
+{
+ const struct hpo_dp_stream_encoder *stream_enc = stream_allocation->hpo_dp_stream_enc;
+
+ if (stream_enc && (stream_enc->id >= ENGINE_ID_HPO_DP_0)) {
+ *src = stream_enc->id - ENGINE_ID_HPO_DP_0;
+ *slots = stream_allocation->slot_count;
+ } else {
+ *src = 0;
+ *slots = 0;
+ }
+}
+
+/* programs DP VC payload allocation */
+void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
+ struct hpo_dp_link_encoder *enc,
+ const struct link_mst_stream_allocation_table *table)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ uint32_t slots = 0;
+ uint32_t src = 0;
+
+ /* --- Set MSE Stream Attribute -
+ * Setup VC Payload Table on Tx Side,
+ * Issue allocation change trigger
+ * to commit payload on both tx and rx side
+ */
+
+ /* we should clean-up table each time */
+
+ if (table->stream_count >= 1) {
+ fill_stream_allocation_row_info(
+ &table->stream_allocations[0],
+ &src,
+ &slots);
+ } else {
+ src = 0;
+ slots = 0;
+ }
+
+ REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC0,
+ SAT_STREAM_SOURCE, src,
+ SAT_SLOT_COUNT, slots);
+
+ if (table->stream_count >= 2) {
+ fill_stream_allocation_row_info(
+ &table->stream_allocations[1],
+ &src,
+ &slots);
+ } else {
+ src = 0;
+ slots = 0;
+ }
+
+ REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC1,
+ SAT_STREAM_SOURCE, src,
+ SAT_SLOT_COUNT, slots);
+
+ if (table->stream_count >= 3) {
+ fill_stream_allocation_row_info(
+ &table->stream_allocations[2],
+ &src,
+ &slots);
+ } else {
+ src = 0;
+ slots = 0;
+ }
+
+ REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC2,
+ SAT_STREAM_SOURCE, src,
+ SAT_SLOT_COUNT, slots);
+
+ if (table->stream_count >= 4) {
+ fill_stream_allocation_row_info(
+ &table->stream_allocations[3],
+ &src,
+ &slots);
+ } else {
+ src = 0;
+ slots = 0;
+ }
+
+ REG_UPDATE_2(DP_DPHY_SYM32_SAT_VC3,
+ SAT_STREAM_SOURCE, src,
+ SAT_SLOT_COUNT, slots);
+
+ /* --- wait for transaction finish */
+
+ /* send allocation change trigger (ACT)
+ * this step first sends the ACT,
+ * then double buffers the SAT into the hardware
+ * making the new allocation active on the DP MST mode link
+ */
+
+ /* SAT_UPDATE:
+ * 0 - No Action
+ * 1 - Update SAT with trigger
+ * 2 - Update SAT without trigger
+ */
+ REG_UPDATE(DP_DPHY_SYM32_SAT_UPDATE,
+ SAT_UPDATE, 1);
+
+ /* wait for update to complete
+ * (i.e. SAT_UPDATE_PENDING field is set to 0)
+ * No need for HW to enforce keepout.
+ */
+ /* Best case and worst case wait time for SAT_UPDATE_PENDING
+ * best: 109 us
+ * worst: 868 us
+ */
+ REG_WAIT(DP_DPHY_SYM32_STATUS,
+ SAT_UPDATE_PENDING, 0,
+ 100, DP_SAT_UPDATE_MAX_RETRY);
+}
+
+void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(
+ struct hpo_dp_link_encoder *enc,
+ uint32_t stream_encoder_inst,
+ struct fixed31_32 avg_time_slots_per_mtp)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ uint32_t x = dc_fixpt_floor(
+ avg_time_slots_per_mtp);
+ uint32_t y = dc_fixpt_ceil(
+ dc_fixpt_shl(
+ dc_fixpt_sub_int(
+ avg_time_slots_per_mtp,
+ x),
+ 25));
+
+ // If y rounds up to integer, carry it over to x.
+ if (y >> 25) {
+ x += 1;
+ y = 0;
+ }
+
+ switch (stream_encoder_inst) {
+ case 0:
+ REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, 0,
+ STREAM_VC_RATE_X, x,
+ STREAM_VC_RATE_Y, y);
+ break;
+ case 1:
+ REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, 0,
+ STREAM_VC_RATE_X, x,
+ STREAM_VC_RATE_Y, y);
+ break;
+ case 2:
+ REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, 0,
+ STREAM_VC_RATE_X, x,
+ STREAM_VC_RATE_Y, y);
+ break;
+ case 3:
+ REG_SET_2(DP_DPHY_SYM32_VC_RATE_CNTL3, 0,
+ STREAM_VC_RATE_X, x,
+ STREAM_VC_RATE_Y, y);
+ break;
+ default:
+ ASSERT(0);
+ }
+
+ /* Best case and worst case wait time for RATE_UPDATE_PENDING
+ * best: 116 ns
+ * worst: 903 ns
+ */
+ /* wait for update to be completed on the link */
+ REG_WAIT(DP_DPHY_SYM32_STATUS,
+ RATE_UPDATE_PENDING, 0,
+ 1, 10);
+}
+
+static bool dcn31_hpo_dp_link_enc_is_in_alt_mode(
+ struct hpo_dp_link_encoder *enc)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ uint32_t dp_alt_mode_disable = 0;
+
+ ASSERT((enc->transmitter >= TRANSMITTER_UNIPHY_A) && (enc->transmitter <= TRANSMITTER_UNIPHY_E));
+
+ /* if value == 1 alt mode is disabled, otherwise it is enabled */
+ REG_GET(RDPCSTX_PHY_CNTL6[enc->transmitter], RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
+ return (dp_alt_mode_disable == 0);
+}
+
+void dcn31_hpo_dp_link_enc_read_state(
+ struct hpo_dp_link_encoder *enc,
+ struct hpo_dp_link_enc_state *state)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+
+ ASSERT(state);
+
+ REG_GET(DP_DPHY_SYM32_STATUS,
+ STATUS, &state->link_enc_enabled);
+ REG_GET(DP_DPHY_SYM32_CONTROL,
+ NUM_LANES, &state->lane_count);
+ REG_GET(DP_DPHY_SYM32_CONTROL,
+ MODE, (uint32_t *)&state->link_mode);
+
+ REG_GET_2(DP_DPHY_SYM32_SAT_VC0,
+ SAT_STREAM_SOURCE, &state->stream_src[0],
+ SAT_SLOT_COUNT, &state->slot_count[0]);
+ REG_GET_2(DP_DPHY_SYM32_SAT_VC1,
+ SAT_STREAM_SOURCE, &state->stream_src[1],
+ SAT_SLOT_COUNT, &state->slot_count[1]);
+ REG_GET_2(DP_DPHY_SYM32_SAT_VC2,
+ SAT_STREAM_SOURCE, &state->stream_src[2],
+ SAT_SLOT_COUNT, &state->slot_count[2]);
+ REG_GET_2(DP_DPHY_SYM32_SAT_VC3,
+ SAT_STREAM_SOURCE, &state->stream_src[3],
+ SAT_SLOT_COUNT, &state->slot_count[3]);
+
+ REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0,
+ STREAM_VC_RATE_X, &state->vc_rate_x[0],
+ STREAM_VC_RATE_Y, &state->vc_rate_y[0]);
+ REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1,
+ STREAM_VC_RATE_X, &state->vc_rate_x[1],
+ STREAM_VC_RATE_Y, &state->vc_rate_y[1]);
+ REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2,
+ STREAM_VC_RATE_X, &state->vc_rate_x[2],
+ STREAM_VC_RATE_Y, &state->vc_rate_y[2]);
+ REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL3,
+ STREAM_VC_RATE_X, &state->vc_rate_x[3],
+ STREAM_VC_RATE_Y, &state->vc_rate_y[3]);
+}
+
+static enum bp_result link_transmitter_control(
+ struct dcn31_hpo_dp_link_encoder *enc3,
+ struct bp_transmitter_control *cntl)
+{
+ enum bp_result result;
+ struct dc_bios *bp = enc3->base.ctx->dc_bios;
+
+ result = bp->funcs->transmitter_control(bp, cntl);
+
+ return result;
+}
+
+/* enables DP PHY output for 128b132b encoding */
+void dcn31_hpo_dp_link_enc_enable_dp_output(
+ struct hpo_dp_link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+ enum transmitter transmitter,
+ enum hpd_source_id hpd_source)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ struct bp_transmitter_control cntl = { 0 };
+ enum bp_result result;
+
+ /* Set the transmitter */
+ enc3->base.transmitter = transmitter;
+
+ /* Set the hpd source */
+ enc3->base.hpd_source = hpd_source;
+
+ /* Enable the PHY */
+ cntl.action = TRANSMITTER_CONTROL_ENABLE;
+ cntl.engine_id = ENGINE_ID_UNKNOWN;
+ cntl.transmitter = enc3->base.transmitter;
+ //cntl.pll_id = clock_source;
+ cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
+ cntl.lanes_number = link_settings->lane_count;
+ cntl.hpd_sel = enc3->base.hpd_source;
+ cntl.pixel_clock = link_settings->link_rate * 1000;
+ cntl.color_depth = COLOR_DEPTH_UNDEFINED;
+ cntl.hpo_engine_id = enc->inst + ENGINE_ID_HPO_DP_0;
+
+ result = link_transmitter_control(enc3, &cntl);
+
+ if (result != BP_RESULT_OK) {
+ DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+ __func__);
+ BREAK_TO_DEBUGGER();
+ }
+}
+
+void dcn31_hpo_dp_link_enc_disable_output(
+ struct hpo_dp_link_encoder *enc,
+ enum signal_type signal)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ struct bp_transmitter_control cntl = { 0 };
+ enum bp_result result;
+
+ /* disable transmitter */
+ cntl.action = TRANSMITTER_CONTROL_DISABLE;
+ cntl.transmitter = enc3->base.transmitter;
+ cntl.hpd_sel = enc3->base.hpd_source;
+ cntl.signal = signal;
+
+ result = link_transmitter_control(enc3, &cntl);
+
+ if (result != BP_RESULT_OK) {
+ DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+ __func__);
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ /* disable encoder */
+ dcn31_hpo_dp_link_enc_disable(enc);
+}
+
+void dcn31_hpo_dp_link_enc_set_ffe(
+ struct hpo_dp_link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+ uint8_t ffe_preset)
+{
+ struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc);
+ struct bp_transmitter_control cntl = { 0 };
+ enum bp_result result;
+
+ /* disable transmitter */
+ cntl.transmitter = enc3->base.transmitter;
+ cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
+ cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
+ cntl.lanes_number = link_settings->lane_count;
+ cntl.pixel_clock = link_settings->link_rate * 1000;
+ cntl.lane_settings = ffe_preset;
+
+ result = link_transmitter_control(enc3, &cntl);
+
+ if (result != BP_RESULT_OK) {
+ DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+ __func__);
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+}
+
+static struct hpo_dp_link_encoder_funcs dcn31_hpo_dp_link_encoder_funcs = {
+ .enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output,
+ .disable_link_phy = dcn31_hpo_dp_link_enc_disable_output,
+ .link_enable = dcn31_hpo_dp_link_enc_enable,
+ .link_disable = dcn31_hpo_dp_link_enc_disable,
+ .set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern,
+ .update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table,
+ .set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size,
+ .is_in_alt_mode = dcn31_hpo_dp_link_enc_is_in_alt_mode,
+ .read_state = dcn31_hpo_dp_link_enc_read_state,
+ .set_ffe = dcn31_hpo_dp_link_enc_set_ffe,
+};
+
+void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+ const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+ const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask)
+{
+ enc31->base.ctx = ctx;
+
+ enc31->base.inst = inst;
+ enc31->base.funcs = &dcn31_hpo_dp_link_encoder_funcs;
+ enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN;
+ enc31->base.transmitter = TRANSMITTER_UNKNOWN;
+
+ enc31->regs = hpo_le_regs;
+ enc31->hpo_le_shift = hpo_le_shift;
+ enc31->hpo_le_mask = hpo_le_mask;
+}
--- /dev/null
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DCN31_HPO_DP_LINK_ENCODER_H__
+#define __DAL_DCN31_HPO_DP_LINK_ENCODER_H__
+
+#include "link_encoder.h"
+
+
+#define DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(hpo_dp_link_encoder)\
+ container_of(hpo_dp_link_encoder, struct dcn31_hpo_dp_link_encoder, base)
+
+
+#define DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id) \
+ SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
+ SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
+ SRI(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
+
+#define DCN3_1_RDPCSTX_REG_LIST(id) \
+ SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
+
+
+#define DCN3_1_HPO_DP_LINK_ENC_REGS \
+ uint32_t DP_LINK_ENC_CLOCK_CONTROL;\
+ uint32_t DP_DPHY_SYM32_CONTROL;\
+ uint32_t DP_DPHY_SYM32_STATUS;\
+ uint32_t DP_DPHY_SYM32_TP_CONFIG;\
+ uint32_t DP_DPHY_SYM32_TP_PRBS_SEED0;\
+ uint32_t DP_DPHY_SYM32_TP_PRBS_SEED1;\
+ uint32_t DP_DPHY_SYM32_TP_PRBS_SEED2;\
+ uint32_t DP_DPHY_SYM32_TP_PRBS_SEED3;\
+ uint32_t DP_DPHY_SYM32_TP_SQ_PULSE;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM0;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM1;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM2;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM3;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM4;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM5;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM6;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM7;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM8;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM9;\
+ uint32_t DP_DPHY_SYM32_TP_CUSTOM10;\
+ uint32_t DP_DPHY_SYM32_SAT_VC0;\
+ uint32_t DP_DPHY_SYM32_SAT_VC1;\
+ uint32_t DP_DPHY_SYM32_SAT_VC2;\
+ uint32_t DP_DPHY_SYM32_SAT_VC3;\
+ uint32_t DP_DPHY_SYM32_VC_RATE_CNTL0;\
+ uint32_t DP_DPHY_SYM32_VC_RATE_CNTL1;\
+ uint32_t DP_DPHY_SYM32_VC_RATE_CNTL2;\
+ uint32_t DP_DPHY_SYM32_VC_RATE_CNTL3;\
+ uint32_t DP_DPHY_SYM32_SAT_UPDATE
+
+struct dcn31_hpo_dp_link_encoder_registers {
+ DCN3_1_HPO_DP_LINK_ENC_REGS;
+ uint32_t RDPCSTX_PHY_CNTL6[5];
+};
+
+#define DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+ SE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh)\
+ SE_SF(DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_RESET, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, DPHY_ENABLE, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, PRECODER_ENABLE, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, NUM_LANES, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, STATUS, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, SAT_UPDATE_PENDING, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS, RATE_UPDATE_PENDING, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0, TP_CUSTOM, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT0, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT1, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT2, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_SELECT3, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL0, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL1, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL2, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG, TP_PRBS_SEL3, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE, TP_SQ_PULSE_WIDTH, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_STREAM_SOURCE, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0, SAT_SLOT_COUNT, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_X, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0, STREAM_VC_RATE_Y, mask_sh),\
+ SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE, SAT_UPDATE, mask_sh)
+
+#define DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(mask_sh)\
+ DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(mask_sh),\
+ DCN3_1_HPO_DP_LINK_ENC_RDPCSTX_MASK_SH_LIST(mask_sh)\
+
+#define DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(type) \
+ type DP_LINK_ENC_CLOCK_EN;\
+ type DPHY_RESET;\
+ type DPHY_ENABLE;\
+ type PRECODER_ENABLE;\
+ type NUM_LANES;\
+ type MODE;\
+ type STATUS;\
+ type SAT_UPDATE_PENDING;\
+ type RATE_UPDATE_PENDING;\
+ type TP_CUSTOM;\
+ type TP_SELECT0;\
+ type TP_SELECT1;\
+ type TP_SELECT2;\
+ type TP_SELECT3;\
+ type TP_PRBS_SEL0;\
+ type TP_PRBS_SEL1;\
+ type TP_PRBS_SEL2;\
+ type TP_PRBS_SEL3;\
+ type TP_SQ_PULSE_WIDTH;\
+ type SAT_STREAM_SOURCE;\
+ type SAT_SLOT_COUNT;\
+ type STREAM_VC_RATE_X;\
+ type STREAM_VC_RATE_Y;\
+ type SAT_UPDATE;\
+ type RDPCS_PHY_DPALT_DISABLE
+
+
+struct dcn31_hpo_dp_link_encoder_shift {
+ DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn31_hpo_dp_link_encoder_mask {
+ DCN3_1_HPO_DP_LINK_ENC_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn31_hpo_dp_link_encoder {
+ struct hpo_dp_link_encoder base;
+ const struct dcn31_hpo_dp_link_encoder_registers *regs;
+ const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift;
+ const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask;
+};
+
+void hpo_dp_link_encoder31_construct(struct dcn31_hpo_dp_link_encoder *enc31,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs,
+ const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift,
+ const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask);
+
+void dcn31_hpo_dp_link_enc_enable_dp_output(
+ struct hpo_dp_link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+ enum transmitter transmitter,
+ enum hpd_source_id hpd_source);
+
+void dcn31_hpo_dp_link_enc_disable_output(
+ struct hpo_dp_link_encoder *enc,
+ enum signal_type signal);
+
+void dcn31_hpo_dp_link_enc_enable(
+ struct hpo_dp_link_encoder *enc,
+ enum dc_lane_count num_lanes);
+
+void dcn31_hpo_dp_link_enc_disable(
+ struct hpo_dp_link_encoder *enc);
+
+void dcn31_hpo_dp_link_enc_set_link_test_pattern(
+ struct hpo_dp_link_encoder *enc,
+ struct encoder_set_dp_phy_pattern_param *tp_params);
+
+void dcn31_hpo_dp_link_enc_update_stream_allocation_table(
+ struct hpo_dp_link_encoder *enc,
+ const struct link_mst_stream_allocation_table *table);
+
+void dcn31_hpo_dp_link_enc_set_throttled_vcp_size(
+ struct hpo_dp_link_encoder *enc,
+ uint32_t stream_encoder_inst,
+ struct fixed31_32 avg_time_slots_per_mtp);
+
+void dcn31_hpo_dp_link_enc_read_state(
+ struct hpo_dp_link_encoder *enc,
+ struct hpo_dp_link_enc_state *state);
+
+void dcn31_hpo_dp_link_enc_set_ffe(
+ struct hpo_dp_link_encoder *enc,
+ const struct dc_link_settings *link_settings,
+ uint8_t ffe_preset);
+
+#endif // __DAL_DCN31_HPO_LINK_ENCODER_H__
--- /dev/null
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dc_bios_types.h"
+#include "dcn31_hpo_dp_stream_encoder.h"
+#include "reg_helper.h"
+#include "dc.h"
+
+#define DC_LOGGER \
+ enc3->base.ctx->logger
+
+#define REG(reg)\
+ (enc3->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ enc3->hpo_se_shift->field_name, enc3->hpo_se_mask->field_name
+
+#define CTX \
+ enc3->base.ctx
+
+
+enum dp2_pixel_encoding {
+ DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444,
+ DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422,
+ DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420,
+ DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY
+};
+
+enum dp2_uncompressed_component_depth {
+ DP_SYM32_ENC_COMPONENT_DEPTH_6BPC,
+ DP_SYM32_ENC_COMPONENT_DEPTH_8BPC,
+ DP_SYM32_ENC_COMPONENT_DEPTH_10BPC,
+ DP_SYM32_ENC_COMPONENT_DEPTH_12BPC
+};
+
+
+static void dcn31_hpo_dp_stream_enc_enable_stream(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Enable all clocks in the DP_STREAM_ENC */
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,
+ DP_STREAM_ENC_CLOCK_EN, 1);
+
+ /* Assert reset to the DP_SYM32_ENC logic */
+ REG_UPDATE(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_RESET, 1);
+ /* Wait for reset to complete (to assert) */
+ REG_WAIT(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_RESET_DONE, 1,
+ 1, 10);
+
+ /* De-assert reset to the DP_SYM32_ENC logic */
+ REG_UPDATE(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_RESET, 0);
+ /* Wait for reset to de-assert */
+ REG_WAIT(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_RESET_DONE, 0,
+ 1, 10);
+
+ /* Enable idle pattern generation */
+ REG_UPDATE(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_ENABLE, 1);
+}
+
+static void dcn31_hpo_dp_stream_enc_dp_unblank(
+ struct hpo_dp_stream_encoder *enc,
+ uint32_t stream_source)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Set the input mux for video stream source */
+ REG_UPDATE(DP_STREAM_ENC_INPUT_MUX_CONTROL,
+ DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, stream_source);
+
+ /* Enable video transmission in main framer */
+ REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,
+ VID_STREAM_ENABLE, 1);
+
+ /* Reset and Enable Pixel to Symbol FIFO */
+ REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
+ PIXEL_TO_SYMBOL_FIFO_RESET, 1);
+ REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL,
+ PIXEL_TO_SYMBOL_FIFO_RESET_DONE, 1,
+ 1, 10);
+ REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
+ PIXEL_TO_SYMBOL_FIFO_RESET, 0);
+ REG_WAIT(DP_SYM32_ENC_VID_FIFO_CONTROL, /* Disable Clock Ramp Adjuster FIFO */
+ PIXEL_TO_SYMBOL_FIFO_RESET_DONE, 0,
+ 1, 10);
+ REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
+ PIXEL_TO_SYMBOL_FIFO_ENABLE, 1);
+
+ /* Reset and Enable Clock Ramp Adjuster FIFO */
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_RESET, 1);
+ REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_RESET_DONE, 1,
+ 1, 10);
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_RESET, 0);
+ REG_WAIT(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_RESET_DONE, 0,
+ 1, 10);
+
+ /* For Debug -- Enable CRC */
+ REG_UPDATE_2(DP_SYM32_ENC_VID_CRC_CONTROL,
+ CRC_ENABLE, 1,
+ CRC_CONT_MODE_ENABLE, 1);
+
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_ENABLE, 1);
+}
+
+static void dcn31_hpo_dp_stream_enc_dp_blank(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Disable video transmission */
+ REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,
+ VID_STREAM_ENABLE, 0);
+
+ /* Wait for video stream transmission disabled
+ * Larger delay to wait until VBLANK - use max retry of
+ * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode +
+ * a little more because we may not trust delay accuracy.
+ */
+ REG_WAIT(DP_SYM32_ENC_VID_STREAM_CONTROL,
+ VID_STREAM_STATUS, 0,
+ 10, 5000);
+
+ /* Disable SDP transmission */
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 0);
+
+ /* Disable Pixel to Symbol FIFO */
+ REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,
+ PIXEL_TO_SYMBOL_FIFO_ENABLE, 0);
+
+ /* Disable Clock Ramp Adjuster FIFO */
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,
+ FIFO_ENABLE, 0);
+}
+
+static void dcn31_hpo_dp_stream_enc_disable(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Disable DP_SYM32_ENC */
+ REG_UPDATE(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_ENABLE, 0);
+
+ /* Disable clocks in the DP_STREAM_ENC */
+ REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,
+ DP_STREAM_ENC_CLOCK_EN, 0);
+}
+
+static void dcn31_hpo_dp_stream_enc_set_stream_attribute(
+ struct hpo_dp_stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space,
+ bool use_vsc_sdp_for_colorimetry,
+ bool compressed_format,
+ bool double_buffer_en)
+{
+ enum dp2_pixel_encoding pixel_encoding;
+ enum dp2_uncompressed_component_depth component_depth;
+ uint32_t h_active_start;
+ uint32_t v_active_start;
+ uint32_t h_blank;
+ uint32_t h_back_porch;
+ uint32_t h_width;
+ uint32_t v_height;
+ uint64_t v_freq;
+ uint8_t misc0 = 0;
+ uint8_t misc1 = 0;
+ uint8_t hsp;
+ uint8_t vsp;
+
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+ struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
+
+ /* MISC0[0] = 0 video and link clocks are asynchronous
+ * MISC1[0] = 0 interlace not supported
+ * MISC1[2:1] = 0 stereo field is handled by hardware
+ * MISC1[5:3] = 0 Reserved
+ */
+
+ /* Interlaced not supported */
+ if (hw_crtc_timing.flags.INTERLACE) {
+ BREAK_TO_DEBUGGER();
+ }
+
+ /* Double buffer enable for MSA and pixel format registers
+ * Only double buffer for changing stream attributes for active streams
+ * Do not double buffer when initially enabling a stream
+ */
+ REG_UPDATE(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL,
+ MSA_DOUBLE_BUFFER_ENABLE, double_buffer_en);
+ REG_UPDATE(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL,
+ PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, double_buffer_en);
+
+ /* Pixel Encoding */
+ switch (hw_crtc_timing.pixel_encoding) {
+ case PIXEL_ENCODING_YCBCR422:
+ pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422;
+ misc0 = misc0 | 0x2; // MISC0[2:1] = 01
+ break;
+ case PIXEL_ENCODING_YCBCR444:
+ pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444;
+ misc0 = misc0 | 0x4; // MISC0[2:1] = 10
+
+ if (hw_crtc_timing.flags.Y_ONLY) {
+ pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY;
+ if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) {
+ /* HW testing only, no use case yet.
+ * Color depth of Y-only could be
+ * 8, 10, 12, 16 bits
+ */
+ misc1 = misc1 | 0x80; // MISC1[7] = 1
+ }
+ }
+ break;
+ case PIXEL_ENCODING_YCBCR420:
+ pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420;
+ misc1 = misc1 | 0x40; // MISC1[6] = 1
+ break;
+ case PIXEL_ENCODING_RGB:
+ default:
+ pixel_encoding = DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444;
+ break;
+ }
+
+ /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
+ * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
+ * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
+ * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
+ */
+ if (use_vsc_sdp_for_colorimetry)
+ misc1 = misc1 | 0x40;
+ else
+ misc1 = misc1 & ~0x40;
+
+ /* Color depth */
+ switch (hw_crtc_timing.display_color_depth) {
+ case COLOR_DEPTH_666:
+ component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
+ // MISC0[7:5] = 000
+ break;
+ case COLOR_DEPTH_888:
+ component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_8BPC;
+ misc0 = misc0 | 0x20; // MISC0[7:5] = 001
+ break;
+ case COLOR_DEPTH_101010:
+ component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_10BPC;
+ misc0 = misc0 | 0x40; // MISC0[7:5] = 010
+ break;
+ case COLOR_DEPTH_121212:
+ component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_12BPC;
+ misc0 = misc0 | 0x60; // MISC0[7:5] = 011
+ break;
+ default:
+ component_depth = DP_SYM32_ENC_COMPONENT_DEPTH_6BPC;
+ break;
+ }
+
+ REG_UPDATE_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,
+ PIXEL_ENCODING_TYPE, compressed_format,
+ UNCOMPRESSED_PIXEL_ENCODING, pixel_encoding,
+ UNCOMPRESSED_COMPONENT_DEPTH, component_depth);
+
+ switch (output_color_space) {
+ case COLOR_SPACE_SRGB:
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ break;
+ case COLOR_SPACE_SRGB_LIMITED:
+ misc0 = misc0 | 0x8; /* bit3=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ break;
+ case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
+ misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
+ misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
+ case COLOR_SPACE_2020_YCBCR:
+ case COLOR_SPACE_XR_RGB:
+ case COLOR_SPACE_MSREF_SCRGB:
+ case COLOR_SPACE_ADOBERGB:
+ case COLOR_SPACE_DCIP3:
+ case COLOR_SPACE_XV_YCC_709:
+ case COLOR_SPACE_XV_YCC_601:
+ case COLOR_SPACE_DISPLAYNATIVE:
+ case COLOR_SPACE_DOLBYVISION:
+ case COLOR_SPACE_APPCTRL:
+ case COLOR_SPACE_CUSTOMPOINTS:
+ case COLOR_SPACE_UNKNOWN:
+ case COLOR_SPACE_YCBCR709_BLACK:
+ /* do nothing */
+ break;
+ }
+
+ /* calculate from vesa timing parameters
+ * h_active_start related to leading edge of sync
+ */
+ h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
+ hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
+
+ h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
+ hw_crtc_timing.h_sync_width;
+
+ /* start at beginning of left border */
+ h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
+
+ v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
+ hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
+ hw_crtc_timing.v_front_porch;
+
+ h_width = hw_crtc_timing.h_border_left + hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right;
+ v_height = hw_crtc_timing.v_border_top + hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom;
+ hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0 : 0x80;
+ vsp = hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 0 : 0x80;
+ v_freq = (uint64_t)hw_crtc_timing.pix_clk_100hz * 100;
+
+ /* MSA Packet Mapping to 32-bit Link Symbols - DP2 spec, section 2.7.4.1
+ *
+ * Lane 0 Lane 1 Lane 2 Lane 3
+ * MSA[0] = { 0, 0, 0, VFREQ[47:40]}
+ * MSA[1] = { 0, 0, 0, VFREQ[39:32]}
+ * MSA[2] = { 0, 0, 0, VFREQ[31:24]}
+ * MSA[3] = { HTotal[15:8], HStart[15:8], HWidth[15:8], VFREQ[23:16]}
+ * MSA[4] = { HTotal[ 7:0], HStart[ 7:0], HWidth[ 7:0], VFREQ[15: 8]}
+ * MSA[5] = { VTotal[15:8], VStart[15:8], VHeight[15:8], VFREQ[ 7: 0]}
+ * MSA[6] = { VTotal[ 7:0], VStart[ 7:0], VHeight[ 7:0], MISC0[ 7: 0]}
+ * MSA[7] = { HSP|HSW[14:8], VSP|VSW[14:8], 0, MISC1[ 7: 0]}
+ * MSA[8] = { HSW[ 7:0], VSW[ 7:0], 0, 0}
+ */
+ REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0,
+ MSA_DATA_LANE_0, 0,
+ MSA_DATA_LANE_1, 0,
+ MSA_DATA_LANE_2, 0,
+ MSA_DATA_LANE_3, v_freq >> 40);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0,
+ MSA_DATA_LANE_0, 0,
+ MSA_DATA_LANE_1, 0,
+ MSA_DATA_LANE_2, 0,
+ MSA_DATA_LANE_3, (v_freq >> 32) & 0xff);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0,
+ MSA_DATA_LANE_0, 0,
+ MSA_DATA_LANE_1, 0,
+ MSA_DATA_LANE_2, 0,
+ MSA_DATA_LANE_3, (v_freq >> 24) & 0xff);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0,
+ MSA_DATA_LANE_0, hw_crtc_timing.h_total >> 8,
+ MSA_DATA_LANE_1, h_active_start >> 8,
+ MSA_DATA_LANE_2, h_width >> 8,
+ MSA_DATA_LANE_3, (v_freq >> 16) & 0xff);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0,
+ MSA_DATA_LANE_0, hw_crtc_timing.h_total & 0xff,
+ MSA_DATA_LANE_1, h_active_start & 0xff,
+ MSA_DATA_LANE_2, h_width & 0xff,
+ MSA_DATA_LANE_3, (v_freq >> 8) & 0xff);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0,
+ MSA_DATA_LANE_0, hw_crtc_timing.v_total >> 8,
+ MSA_DATA_LANE_1, v_active_start >> 8,
+ MSA_DATA_LANE_2, v_height >> 8,
+ MSA_DATA_LANE_3, v_freq & 0xff);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0,
+ MSA_DATA_LANE_0, hw_crtc_timing.v_total & 0xff,
+ MSA_DATA_LANE_1, v_active_start & 0xff,
+ MSA_DATA_LANE_2, v_height & 0xff,
+ MSA_DATA_LANE_3, misc0);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0,
+ MSA_DATA_LANE_0, hsp | (hw_crtc_timing.h_sync_width >> 8),
+ MSA_DATA_LANE_1, vsp | (hw_crtc_timing.v_sync_width >> 8),
+ MSA_DATA_LANE_2, 0,
+ MSA_DATA_LANE_3, misc1);
+
+ REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0,
+ MSA_DATA_LANE_0, hw_crtc_timing.h_sync_width & 0xff,
+ MSA_DATA_LANE_1, hw_crtc_timing.v_sync_width & 0xff,
+ MSA_DATA_LANE_2, 0,
+ MSA_DATA_LANE_3, 0);
+}
+
+static void dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num(
+ struct hpo_dp_stream_encoder *enc,
+ struct encoder_info_frame *info_frame)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ if (info_frame->adaptive_sync.valid == true &&
+ info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {
+ //00: REFER_TO_DP_SOF, 01: REFER_TO_OTG_SOF
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, 1);
+
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER,
+ info_frame->sdp_line_num.adaptive_sync_line_num);
+ }
+}
+
+static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(
+ struct hpo_dp_stream_encoder *enc,
+ const struct encoder_info_frame *info_frame)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+ uint32_t dmdata_packet_enabled = 0;
+
+ if (info_frame->vsc.valid)
+ enc->vpg->funcs->update_generic_info_packet(
+ enc->vpg,
+ 0, /* packetIndex */
+ &info_frame->vsc,
+ true);
+
+ if (info_frame->spd.valid)
+ enc->vpg->funcs->update_generic_info_packet(
+ enc->vpg,
+ 2, /* packetIndex */
+ &info_frame->spd,
+ true);
+
+ if (info_frame->hdrsmd.valid)
+ enc->vpg->funcs->update_generic_info_packet(
+ enc->vpg,
+ 3, /* packetIndex */
+ &info_frame->hdrsmd,
+ true);
+
+ /* packetIndex 4 is used for send immediate sdp message, and please
+ * use other packetIndex (such as 5,6) for other info packet
+ */
+
+ if (info_frame->adaptive_sync.valid)
+ enc->vpg->funcs->update_generic_info_packet(
+ enc->vpg,
+ 5, /* packetIndex */
+ &info_frame->adaptive_sync,
+ true);
+
+ /* enable/disable transmission of packet(s).
+ * If enabled, packet transmission begins on the next frame
+ */
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->vsc.valid);
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->spd.valid);
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->hdrsmd.valid);
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->adaptive_sync.valid);
+
+ /* check if dynamic metadata packet transmission is enabled */
+ REG_GET(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL,
+ METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
+
+ /* Enable secondary data path */
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 1);
+}
+
+static void dcn31_hpo_dp_stream_enc_stop_dp_info_packets(
+ struct hpo_dp_stream_encoder *enc)
+{
+ /* stop generic packets on DP */
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+ uint32_t asp_enable = 0;
+ uint32_t atp_enable = 0;
+ uint32_t aip_enable = 0;
+ uint32_t acm_enable = 0;
+
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);
+
+ /* Disable secondary data path if audio is also disabled */
+ REG_GET_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
+ ASP_ENABLE, &asp_enable,
+ ATP_ENABLE, &atp_enable,
+ AIP_ENABLE, &aip_enable,
+ ACM_ENABLE, &acm_enable);
+ if (!(asp_enable || atp_enable || aip_enable || acm_enable))
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 0);
+}
+
+static uint32_t hpo_dp_is_gsp_enabled(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+ uint32_t gsp0_enabled = 0;
+ uint32_t gsp2_enabled = 0;
+ uint32_t gsp3_enabled = 0;
+ uint32_t gsp11_enabled = 0;
+
+ REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp0_enabled);
+ REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp2_enabled);
+ REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp3_enabled);
+ REG_GET(DP_SYM32_ENC_SDP_GSP_CONTROL11, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, &gsp11_enabled);
+
+ return (gsp0_enabled || gsp2_enabled || gsp3_enabled || gsp11_enabled);
+}
+
+static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet(
+ struct hpo_dp_stream_encoder *enc,
+ bool enable,
+ uint8_t *dsc_packed_pps,
+ bool immediate_update)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ if (enable) {
+ struct dc_info_packet pps_sdp;
+ int i;
+
+ /* Configure for PPS packet size (128 bytes) */
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
+ GSP_PAYLOAD_SIZE, 3);
+
+ /* Load PPS into infoframe (SDP) registers */
+ pps_sdp.valid = true;
+ pps_sdp.hb0 = 0;
+ pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
+ pps_sdp.hb2 = 127;
+ pps_sdp.hb3 = 0;
+
+ for (i = 0; i < 4; i++) {
+ memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
+ enc3->base.vpg->funcs->update_generic_info_packet(
+ enc3->base.vpg,
+ 11 + i,
+ &pps_sdp,
+ immediate_update);
+ }
+
+ /* SW should make sure VBID[6] update line number is bigger
+ * than PPS transmit line number
+ */
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
+ GSP_TRANSMISSION_LINE_NUMBER, 2);
+
+ REG_UPDATE_2(DP_SYM32_ENC_VID_VBID_CONTROL,
+ VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, 0,
+ VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, 3);
+
+ /* Send PPS data at the line number specified above. */
+ REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,
+ GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 1);
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 1);
+ } else {
+ /* Disable Generic Stream Packet 11 (GSP) transmission */
+ REG_UPDATE_2(DP_SYM32_ENC_SDP_GSP_CONTROL11,
+ GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0,
+ GSP_PAYLOAD_SIZE, 0);
+ }
+}
+
+static void dcn31_hpo_dp_stream_enc_map_stream_to_link(
+ struct hpo_dp_stream_encoder *enc,
+ uint32_t stream_enc_inst,
+ uint32_t link_enc_inst)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ ASSERT(stream_enc_inst < 4 && link_enc_inst < 2);
+
+ switch (stream_enc_inst) {
+ case 0:
+ REG_UPDATE(DP_STREAM_MAPPER_CONTROL0,
+ DP_STREAM_LINK_TARGET, link_enc_inst);
+ break;
+ case 1:
+ REG_UPDATE(DP_STREAM_MAPPER_CONTROL1,
+ DP_STREAM_LINK_TARGET, link_enc_inst);
+ break;
+ case 2:
+ REG_UPDATE(DP_STREAM_MAPPER_CONTROL2,
+ DP_STREAM_LINK_TARGET, link_enc_inst);
+ break;
+ case 3:
+ REG_UPDATE(DP_STREAM_MAPPER_CONTROL3,
+ DP_STREAM_LINK_TARGET, link_enc_inst);
+ break;
+ }
+}
+
+static void dcn31_hpo_dp_stream_enc_audio_setup(
+ struct hpo_dp_stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *info)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Set the input mux for video stream source */
+ REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL,
+ DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst);
+
+ ASSERT(enc->apg);
+ enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info);
+}
+
+static void dcn31_hpo_dp_stream_enc_audio_enable(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Enable Audio packets */
+ REG_UPDATE(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, 1);
+
+ /* Program the ATP and AIP next */
+ REG_UPDATE_2(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
+ ATP_ENABLE, 1,
+ AIP_ENABLE, 1);
+
+ /* Enable secondary data path */
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 1);
+
+ /* Enable APG block */
+ enc->apg->funcs->enable_apg(enc->apg);
+}
+
+static void dcn31_hpo_dp_stream_enc_audio_disable(
+ struct hpo_dp_stream_encoder *enc)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ /* Disable Audio packets */
+ REG_UPDATE_4(DP_SYM32_ENC_SDP_AUDIO_CONTROL0,
+ ASP_ENABLE, 0,
+ ATP_ENABLE, 0,
+ AIP_ENABLE, 0,
+ ACM_ENABLE, 0);
+
+ /* Disable STP Stream Enable if other SDP GSP are also disabled */
+ if (!(hpo_dp_is_gsp_enabled(enc)))
+ REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, 0);
+
+ /* Disable APG block */
+ enc->apg->funcs->disable_apg(enc->apg);
+}
+
+static void dcn31_hpo_dp_stream_enc_read_state(
+ struct hpo_dp_stream_encoder *enc,
+ struct hpo_dp_stream_encoder_state *s)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ REG_GET(DP_SYM32_ENC_CONTROL,
+ DP_SYM32_ENC_ENABLE, &s->stream_enc_enabled);
+ REG_GET(DP_SYM32_ENC_VID_STREAM_CONTROL,
+ VID_STREAM_ENABLE, &s->vid_stream_enabled);
+ REG_GET(DP_STREAM_ENC_INPUT_MUX_CONTROL,
+ DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, &s->otg_inst);
+
+ REG_GET_3(DP_SYM32_ENC_VID_PIXEL_FORMAT,
+ PIXEL_ENCODING_TYPE, &s->compressed_format,
+ UNCOMPRESSED_PIXEL_ENCODING, &s->pixel_encoding,
+ UNCOMPRESSED_COMPONENT_DEPTH, &s->component_depth);
+
+ REG_GET(DP_SYM32_ENC_SDP_CONTROL,
+ SDP_STREAM_ENABLE, &s->sdp_enabled);
+
+ switch (enc->inst) {
+ case 0:
+ REG_GET(DP_STREAM_MAPPER_CONTROL0,
+ DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
+ break;
+ case 1:
+ REG_GET(DP_STREAM_MAPPER_CONTROL1,
+ DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
+ break;
+ case 2:
+ REG_GET(DP_STREAM_MAPPER_CONTROL2,
+ DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
+ break;
+ case 3:
+ REG_GET(DP_STREAM_MAPPER_CONTROL3,
+ DP_STREAM_LINK_TARGET, &s->mapped_to_link_enc);
+ break;
+ }
+}
+
+static void dcn31_set_hblank_min_symbol_width(
+ struct hpo_dp_stream_encoder *enc,
+ uint16_t width)
+{
+ struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
+
+ REG_SET(DP_SYM32_ENC_HBLANK_CONTROL, 0,
+ HBLANK_MINIMUM_SYMBOL_WIDTH, width);
+}
+
+static const struct hpo_dp_stream_encoder_funcs dcn30_str_enc_funcs = {
+ .enable_stream = dcn31_hpo_dp_stream_enc_enable_stream,
+ .dp_unblank = dcn31_hpo_dp_stream_enc_dp_unblank,
+ .dp_blank = dcn31_hpo_dp_stream_enc_dp_blank,
+ .disable = dcn31_hpo_dp_stream_enc_disable,
+ .set_stream_attribute = dcn31_hpo_dp_stream_enc_set_stream_attribute,
+ .update_dp_info_packets_sdp_line_num = dcn31_hpo_dp_stream_enc_update_dp_info_packets_sdp_line_num,
+ .update_dp_info_packets = dcn31_hpo_dp_stream_enc_update_dp_info_packets,
+ .stop_dp_info_packets = dcn31_hpo_dp_stream_enc_stop_dp_info_packets,
+ .dp_set_dsc_pps_info_packet = dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet,
+ .map_stream_to_link = dcn31_hpo_dp_stream_enc_map_stream_to_link,
+ .dp_audio_setup = dcn31_hpo_dp_stream_enc_audio_setup,
+ .dp_audio_enable = dcn31_hpo_dp_stream_enc_audio_enable,
+ .dp_audio_disable = dcn31_hpo_dp_stream_enc_audio_disable,
+ .read_state = dcn31_hpo_dp_stream_enc_read_state,
+ .set_hblank_min_symbol_width = dcn31_set_hblank_min_symbol_width,
+};
+
+void dcn31_hpo_dp_stream_encoder_construct(
+ struct dcn31_hpo_dp_stream_encoder *enc3,
+ struct dc_context *ctx,
+ struct dc_bios *bp,
+ uint32_t inst,
+ enum engine_id eng_id,
+ struct vpg *vpg,
+ struct apg *apg,
+ const struct dcn31_hpo_dp_stream_encoder_registers *regs,
+ const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
+ const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask)
+{
+ enc3->base.funcs = &dcn30_str_enc_funcs;
+ enc3->base.ctx = ctx;
+ enc3->base.inst = inst;
+ enc3->base.id = eng_id;
+ enc3->base.bp = bp;
+ enc3->base.vpg = vpg;
+ enc3->base.apg = apg;
+ enc3->regs = regs;
+ enc3->hpo_se_shift = hpo_se_shift;
+ enc3->hpo_se_mask = hpo_se_mask;
+}
--- /dev/null
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
+#define __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
+
+#include "dcn30/dcn30_vpg.h"
+#include "dcn31/dcn31_apg.h"
+#include "stream_encoder.h"
+
+
+#define DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_dp_stream_encoder)\
+ container_of(hpo_dp_stream_encoder, struct dcn31_hpo_dp_stream_encoder, base)
+
+
+/* Define MSA_DATA_LANE_[0-3] fields to make programming easier */
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0__SHIFT 0x0
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1__SHIFT 0x8
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2__SHIFT 0x10
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3__SHIFT 0x18
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0_MASK 0x000000FFL
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1_MASK 0x0000FF00L
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2_MASK 0x00FF0000L
+#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3_MASK 0xFF000000L
+
+
+#define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id) \
+ SR(DP_STREAM_MAPPER_CONTROL0),\
+ SR(DP_STREAM_MAPPER_CONTROL1),\
+ SR(DP_STREAM_MAPPER_CONTROL2),\
+ SR(DP_STREAM_MAPPER_CONTROL3),\
+ SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\
+ SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\
+ SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\
+ SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\
+ SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\
+ SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
+ SRI(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
+
+#define DCN3_1_HPO_DP_STREAM_ENC_REGS \
+ uint32_t DP_STREAM_MAPPER_CONTROL0;\
+ uint32_t DP_STREAM_MAPPER_CONTROL1;\
+ uint32_t DP_STREAM_MAPPER_CONTROL2;\
+ uint32_t DP_STREAM_MAPPER_CONTROL3;\
+ uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\
+ uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\
+ uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\
+ uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\
+ uint32_t DP_SYM32_ENC_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\
+ uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_MSA0;\
+ uint32_t DP_SYM32_ENC_VID_MSA1;\
+ uint32_t DP_SYM32_ENC_VID_MSA2;\
+ uint32_t DP_SYM32_ENC_VID_MSA3;\
+ uint32_t DP_SYM32_ENC_VID_MSA4;\
+ uint32_t DP_SYM32_ENC_VID_MSA5;\
+ uint32_t DP_SYM32_ENC_VID_MSA6;\
+ uint32_t DP_SYM32_ENC_VID_MSA7;\
+ uint32_t DP_SYM32_ENC_VID_MSA8;\
+ uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\
+ uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\
+ uint32_t DP_SYM32_ENC_SDP_CONTROL;\
+ uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\
+ uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\
+ uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\
+ uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\
+ uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\
+ uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\
+ uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\
+ uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\
+ uint32_t DP_SYM32_ENC_HBLANK_CONTROL
+
+
+#define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
+ SE_SF(DP_STREAM_MAPPER_CONTROL0, DP_STREAM_LINK_TARGET, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC_CLOCK_EN, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE, mask_sh),\
+ SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET_DONE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, MSA_DOUBLE_BUFFER_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_0, mask_sh),\
+ SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_1, mask_sh),\
+ SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_2, mask_sh),\
+ SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_3, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET_DONE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_STATUS, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL, SDP_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_PAYLOAD_SIZE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, METADATA_PACKET_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AUDIO_MUTE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ATP_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh),\
+ SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
+
+
+#define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
+ type DP_STREAM_LINK_TARGET;\
+ type DP_STREAM_ENC_CLOCK_EN;\
+ type DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL;\
+ type DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
+ type FIFO_RESET;\
+ type FIFO_RESET_DONE;\
+ type FIFO_ENABLE;\
+ type DP_SYM32_ENC_RESET;\
+ type DP_SYM32_ENC_RESET_DONE;\
+ type DP_SYM32_ENC_ENABLE;\
+ type PIXEL_ENCODING_TYPE;\
+ type UNCOMPRESSED_PIXEL_ENCODING;\
+ type UNCOMPRESSED_COMPONENT_DEPTH;\
+ type PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE;\
+ type MSA_DOUBLE_BUFFER_ENABLE;\
+ type MSA_DATA_LANE_0;\
+ type MSA_DATA_LANE_1;\
+ type MSA_DATA_LANE_2;\
+ type MSA_DATA_LANE_3;\
+ type PIXEL_TO_SYMBOL_FIFO_RESET;\
+ type PIXEL_TO_SYMBOL_FIFO_RESET_DONE;\
+ type PIXEL_TO_SYMBOL_FIFO_ENABLE;\
+ type VID_STREAM_ENABLE;\
+ type VID_STREAM_STATUS;\
+ type VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE;\
+ type VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER;\
+ type SDP_STREAM_ENABLE;\
+ type AUDIO_MUTE;\
+ type ASP_ENABLE;\
+ type ATP_ENABLE;\
+ type AIP_ENABLE;\
+ type ACM_ENABLE;\
+ type GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE;\
+ type GSP_PAYLOAD_SIZE;\
+ type GSP_TRANSMISSION_LINE_NUMBER;\
+ type GSP_SOF_REFERENCE;\
+ type METADATA_PACKET_ENABLE;\
+ type CRC_ENABLE;\
+ type CRC_CONT_MODE_ENABLE;\
+ type HBLANK_MINIMUM_SYMBOL_WIDTH
+
+
+struct dcn31_hpo_dp_stream_encoder_registers {
+ DCN3_1_HPO_DP_STREAM_ENC_REGS;
+};
+
+struct dcn31_hpo_dp_stream_encoder_shift {
+ DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn31_hpo_dp_stream_encoder_mask {
+ DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn31_hpo_dp_stream_encoder {
+ struct hpo_dp_stream_encoder base;
+ const struct dcn31_hpo_dp_stream_encoder_registers *regs;
+ const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift;
+ const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask;
+};
+
+
+void dcn31_hpo_dp_stream_encoder_construct(
+ struct dcn31_hpo_dp_stream_encoder *enc3,
+ struct dc_context *ctx,
+ struct dc_bios *bp,
+ uint32_t inst,
+ enum engine_id eng_id,
+ struct vpg *vpg,
+ struct apg *apg,
+ const struct dcn31_hpo_dp_stream_encoder_registers *regs,
+ const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
+ const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
+
+
+#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
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