Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into...

 - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
   MT8195 SoCs
 - Converted most Mediatek clock drivers to struct platform_driver
 - MediaTek clock drivers can be built as modules
 - Mediatek MT8188 SoC clk drivers
 - Clock driver for Sunplus SP7021 SoC
 - Reimplement Loongson-1 clk driver with DT support
 - Clk driver support for Loongson-2 SoCs
 - Migrate socfpga clk driver to of_clk_add_hw_provider()

* clk-mediatek: (84 commits)
  clk: mediatek: fhctl: Mark local variables static
  clk: mediatek: Use right match table, include mod_devicetable
  clk: mediatek: Add MT8188 adsp clock support
  clk: mediatek: Add MT8188 imp i2c wrapper clock support
  clk: mediatek: Add MT8188 wpesys clock support
  clk: mediatek: Add MT8188 vppsys1 clock support
  clk: mediatek: Add MT8188 vppsys0 clock support
  clk: mediatek: Add MT8188 vencsys clock support
  clk: mediatek: Add MT8188 vdosys1 clock support
  clk: mediatek: Add MT8188 vdosys0 clock support
  clk: mediatek: Add MT8188 vdecsys clock support
  clk: mediatek: Add MT8188 mfgcfg clock support
  clk: mediatek: Add MT8188 ipesys clock support
  clk: mediatek: Add MT8188 imgsys clock support
  clk: mediatek: Add MT8188 ccusys clock support
  clk: mediatek: Add MT8188 camsys clock support
  clk: mediatek: Add MT8188 infrastructure clock support
  clk: mediatek: Add MT8188 peripheral clock support
  clk: mediatek: Add MT8188 topckgen clock support
  clk: mediatek: Add MT8188 apmixedsys clock support
  ...

* clk-sunplus:
  clk: Add Sunplus SP7021 clock driver

* clk-loongson:
  clk: clk-loongson2: add clock controller driver support
  dt-bindings: clock: add loongson-2 boot clock index
  MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
  MIPS: loongson32: Update the clock initialization
  clk: loongson1: Re-implement the clock driver
  clk: loongson1: Remove the outdated driver
  dt-bindings: clock: Add Loongson-1 clock

* clk-socfpga:
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/clk/Kconfig
Simple merge

diff --cc drivers/clk/Makefile
Simple merge

diff --cc drivers/clk/mediatek/clk-pllfh.c
index f135b32c6dbedc69eebb5d6516dd9fd41499b914,7b6e051443f4887f205d44b06933656f9b7a49f4,f48780bec5077ae27aad22bd59a654e94734bdcb,f48780bec5077ae27aad22bd59a654e94734bdcb,f48780bec5077ae27aad22bd59a654e94734bdcb..3a2b3f90be25d5925a19890c82823784791dd70a
--- 1/drivers/clk/mediatek/clk-pllfh.c
--- 2/drivers/clk/mediatek/clk-pllfh.c
--- 3/drivers/clk/mediatek/clk-pllfh.c
--- 4/drivers/clk/mediatek/clk-pllfh.c
--- 5/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@@@@@ -102,16 -102,10 -102,9 -102,9 -102,9 +102,17 @@@@@@ void fhctl_parse_dt(const u8 *compatibl
                pllfh->state.ssc_rate = ssc_rate;
                pllfh->state.base = base;
        }
 ++++
 ++++out_node_put:
 ++++   of_node_put(node);
 ++++   return;
 ++++err:
 ++++   iounmap(base);
 ++++   goto out_node_put;
     }
+ +++EXPORT_SYMBOL_GPL(fhctl_parse_dt);
     
- ---static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
+ +++static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
     {
        struct fh_pll_regs *regs = &fh->regs;
        const struct fhctl_offset *offset;