Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into...

 - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
   MT8195 SoCs
 - Converted most Mediatek clock drivers to struct platform_driver
 - MediaTek clock drivers can be built as modules
 - Mediatek MT8188 SoC clk drivers
 - Clock driver for Sunplus SP7021 SoC
 - Reimplement Loongson-1 clk driver with DT support
 - Clk driver support for Loongson-2 SoCs
 - Migrate socfpga clk driver to of_clk_add_hw_provider()

* clk-mediatek: (84 commits)
  clk: mediatek: fhctl: Mark local variables static
  clk: mediatek: Use right match table, include mod_devicetable
  clk: mediatek: Add MT8188 adsp clock support
  clk: mediatek: Add MT8188 imp i2c wrapper clock support
  clk: mediatek: Add MT8188 wpesys clock support
  clk: mediatek: Add MT8188 vppsys1 clock support
  clk: mediatek: Add MT8188 vppsys0 clock support
  clk: mediatek: Add MT8188 vencsys clock support
  clk: mediatek: Add MT8188 vdosys1 clock support
  clk: mediatek: Add MT8188 vdosys0 clock support
  clk: mediatek: Add MT8188 vdecsys clock support
  clk: mediatek: Add MT8188 mfgcfg clock support
  clk: mediatek: Add MT8188 ipesys clock support
  clk: mediatek: Add MT8188 imgsys clock support
  clk: mediatek: Add MT8188 ccusys clock support
  clk: mediatek: Add MT8188 camsys clock support
  clk: mediatek: Add MT8188 infrastructure clock support
  clk: mediatek: Add MT8188 peripheral clock support
  clk: mediatek: Add MT8188 topckgen clock support
  clk: mediatek: Add MT8188 apmixedsys clock support
  ...

* clk-sunplus:
  clk: Add Sunplus SP7021 clock driver

* clk-loongson:
  clk: clk-loongson2: add clock controller driver support
  dt-bindings: clock: add loongson-2 boot clock index
  MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
  MIPS: loongson32: Update the clock initialization
  clk: loongson1: Re-implement the clock driver
  clk: loongson1: Remove the outdated driver
  dt-bindings: clock: Add Loongson-1 clock

* clk-socfpga:
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling

diff --combined MAINTAINERS
index ec57c42ed5440d5d2c6721d30aa0f4a69ec8b44a,8d5bc223f3053bf83c8a5aeaa6900ceafe111179,f72107a6e86f1be55ae1b7ca19ff87af0b63b604,2f676da6b1d32d9ae34b66fe237f580c2da81936,8d5bc223f3053bf83c8a5aeaa6900ceafe111179..ef4d8ef47d5966c837e8def1bd79aeae18b01362
--- 1/MAINTAINERS
--- 2/MAINTAINERS
--- 3/MAINTAINERS
--- 4/MAINTAINERS
--- 5/MAINTAINERS
+++ b/MAINTAINERS
@@@@@@ -2849,6 -2849,6 -2849,7 -2849,6 -2849,6 +2849,7 @@@@@@ F:        Documentation/devicetree/bindings/re
     F: arch/arm/boot/dts/sunplus-sp7021*.dts*
     F: arch/arm/configs/sp7021_*defconfig
     F: arch/arm/mach-sunplus/
++ ++F: drivers/clk/clk-sp7021.c
     F: drivers/irqchip/irq-sp7021-intc.c
     F: drivers/reset/reset-sunplus.c
     F: include/dt-bindings/clock/sunplus,sp7021-clkc.h
@@@@@@ -9871,10 -9871,10 -9872,10 -9871,10 -9871,10 +9872,10 @@@@@@ M:  Christian Brauner <brauner@kernel.or
     M: Seth Forshee <sforshee@kernel.org>
     L: linux-fsdevel@vger.kernel.org
     S: Maintained
 ----T: git://git.kernel.org/pub/scm/linux/kernel/git/vfs/idmapping.git
 ++++T: git git://git.kernel.org/pub/scm/linux/kernel/git/vfs/idmapping.git
     F: Documentation/filesystems/idmappings.rst
 ----F: tools/testing/selftests/mount_setattr/
     F: include/linux/mnt_idmapping.*
 ++++F: tools/testing/selftests/mount_setattr/
     
     IDT VersaClock 5 CLOCK DRIVER
     M: Luca Ceresoli <luca@lucaceresoli.net>
@@@@@@ -12121,6 -12121,6 -12122,6 -12121,7 -12121,6 +12122,7 @@@@@@ M:  Yinbo Zhu <zhuyinbo@loongson.cn
     L: linux-clk@vger.kernel.org
     S: Maintained
     F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ +F: drivers/clk/clk-loongson2.c
     F: include/dt-bindings/clock/loongson,ls2k-clk.h
     
     LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
@@@@@@ -14000,7 -14000,7 -14001,7 -14001,6 -14000,7 +14002,6 @@@@@@ L:  linux-mips@vger.kernel.or
     S: Maintained
     F: arch/mips/include/asm/mach-loongson32/
     F: arch/mips/loongson32/
--- -F: drivers/*/*/*loongson1*
     F: drivers/*/*loongson1*
     
     MIPS/LOONGSON2EF ARCHITECTURE
@@@@@@ -16391,7 -16391,6 -16392,6 -16391,6 -16391,6 +16392,7 @@@@@@ R:  Alexander Shishkin <alexander.shishk
     R: Jiri Olsa <jolsa@kernel.org>
     R: Namhyung Kim <namhyung@kernel.org>
     R: Ian Rogers <irogers@google.com>
 ++++R: Adrian Hunter <adrian.hunter@intel.com>
     L: linux-perf-users@vger.kernel.org
     L: linux-kernel@vger.kernel.org
     S: Supported
@@@@@@ -19864,6 -19863,13 -19864,13 -19863,13 -19863,13 +19865,6 @@@@@@ S:      Maintaine
     W: http://wiki.laptop.org/go/DCON
     F: drivers/staging/olpc_dcon/
     
 ----STAGING - REALTEK RTL8188EU DRIVERS
 ----M: Larry Finger <Larry.Finger@lwfinger.net>
 ----M: Phillip Potter <phil@philpotter.co.uk>
 ----R: Pavel Skripkin <paskripkin@gmail.com>
 ----S: Supported
 ----F: drivers/staging/r8188eu/
 ----
     STAGING - REALTEK RTL8712U DRIVERS
     M: Larry Finger <Larry.Finger@lwfinger.net>
     M: Florian Schilhabel <florian.c.schilhabel@googlemail.com>.

diff --combined drivers/clk/Kconfig
index 4b77f3e2ba88917cafc021b4c527dfd3541fe58b,b6c5bf69a2b2c65aa24c2dfcfb6050c1412708d8,54e01bb2f5685e5473acfdb1014d3cff7144c409,44c08b30c34d71744ebab200d47b336c758e2eb4,b6c5bf69a2b2c65aa24c2dfcfb6050c1412708d8..8f0fa6fdaa44e5bdd86611a633647835dcc78e8d
--- 1/drivers/clk/Kconfig
--- 2/drivers/clk/Kconfig
--- 3/drivers/clk/Kconfig
--- 4/drivers/clk/Kconfig
--- 5/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@@@@@ -325,6 -325,6 -325,6 -325,15 -325,6 +325,15 @@@@@@ config COMMON_CLK_LOCHNAGA
          This driver supports the clocking features of the Cirrus Logic
          Lochnagar audio development board.
     
+++ +config COMMON_CLK_LOONGSON2
+++ +   bool "Clock driver for Loongson-2 SoC"
+++ +   depends on LOONGARCH || COMPILE_TEST
+++ +   help
+++ +          This driver provides support for clock controller on Loongson-2 SoC.
+++ +          The clock controller can generates and supplies clock to various
+++ +          peripherals within the SoC.
+++ +          Say Y here to support Loongson-2 SoC clock driver.
+++ +
     config COMMON_CLK_NXP
        def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
        select REGMAP_MMIO if ARCH_LPC32XX
@@@@@@ -367,15 -367,6 -367,6 -376,6 -367,6 +376,15 @@@@@@ config COMMON_CLK_RS9_PCI
          This driver supports the Renesas 9-series PCIe clock generator
          models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
     
 ++++config COMMON_CLK_SI521XX
 ++++   tristate "Clock driver for SkyWorks Si521xx PCIe clock generators"
 ++++   depends on I2C
 ++++   depends on OF
 ++++   select REGMAP_I2C
 ++++   help
 ++++     This driver supports the SkyWorks Si521xx PCIe clock generator
 ++++     models Si52144/Si52146/Si52147.
 ++++
     config COMMON_CLK_VC5
        tristate "Clock driver for IDT VersaClock 5,6 devices"
        depends on I2C
@@@@@@ -445,6 -436,6 -436,16 -445,6 -436,6 +454,16 @@@@@@ config COMMON_CLK_K21
        help
          Support for the Canaan Kendryte K210 RISC-V SoC clocks.
     
++ ++config COMMON_CLK_SP7021
++ ++   tristate "Clock driver for Sunplus SP7021 SoC"
++ ++   depends on SOC_SP7021 || COMPILE_TEST
++ ++   default SOC_SP7021
++ ++   help
++ ++     This driver supports the Sunplus SP7021 SoC clocks.
++ ++     It implements SP7021 PLLs/gate.
++ ++     Not all features of the PLL are currently supported
++ ++     by the driver.
++ ++
     source "drivers/clk/actions/Kconfig"
     source "drivers/clk/analogbits/Kconfig"
     source "drivers/clk/baikal-t1/Kconfig"

diff --combined drivers/clk/Makefile
index 5e2c225f040c43a34f81030d7896a6db0a6ed320,e3ca0d058a25671f2c391a1a42748358e136256b,7bbf77acf181eee6ed13d50ff2a336effb49328c,fd9d0d51190d1795538b44c18f5995656d94870e,e3ca0d058a25671f2c391a1a42748358e136256b..9b7a414b5614ecbf34065532fa4b02b22c3d1baf
--- 1/drivers/clk/Makefile
--- 2/drivers/clk/Makefile
--- 3/drivers/clk/Makefile
--- 4/drivers/clk/Makefile
--- 5/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@@@@@ -43,6 -43,6 -43,6 -43,8 -43,6 +43,8 @@@@@@ obj-$(CONFIG_COMMON_CLK_K210)         += clk-k
     obj-$(CONFIG_LMK04832)                     += clk-lmk04832.o
     obj-$(CONFIG_COMMON_CLK_LAN966X)   += clk-lan966x.o
     obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
+++ +obj-$(CONFIG_MACH_LOONGSON32)              += clk-loongson1.o
+++ +obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o
     obj-$(CONFIG_COMMON_CLK_MAX77686)  += clk-max77686.o
     obj-$(CONFIG_COMMON_CLK_MAX9485)   += clk-max9485.o
     obj-$(CONFIG_ARCH_MILBEAUT_M10V)   += clk-milbeaut.o
@@@@@@ -65,6 -65,6 -65,7 -67,6 -65,6 +67,7 @@@@@@ obj-$(CONFIG_COMMON_CLK_SI5351)               += clk
     obj-$(CONFIG_COMMON_CLK_SI514)             += clk-si514.o
     obj-$(CONFIG_COMMON_CLK_SI544)             += clk-si544.o
     obj-$(CONFIG_COMMON_CLK_SI570)             += clk-si570.o
++ ++obj-$(CONFIG_COMMON_CLK_SP7021)            += clk-sp7021.o
     obj-$(CONFIG_COMMON_CLK_STM32F)            += clk-stm32f4.o
     obj-$(CONFIG_COMMON_CLK_STM32H7)   += clk-stm32h7.o
     obj-$(CONFIG_COMMON_CLK_STM32MP157)        += clk-stm32mp1.o
@@@@@@ -72,7 -72,6 -73,6 -74,6 -72,6 +75,7 @@@@@@ obj-$(CONFIG_COMMON_CLK_TPS68470)      
     obj-$(CONFIG_CLK_TWL6040)          += clk-twl6040.o
     obj-$(CONFIG_ARCH_VT8500)          += clk-vt8500.o
     obj-$(CONFIG_COMMON_CLK_RS9_PCIE)  += clk-renesas-pcie.o
 ++++obj-$(CONFIG_COMMON_CLK_SI521XX)   += clk-si521xx.o
     obj-$(CONFIG_COMMON_CLK_VC5)               += clk-versaclock5.o
     obj-$(CONFIG_COMMON_CLK_VC7)               += clk-versaclock7.o
     obj-$(CONFIG_COMMON_CLK_WM831X)            += clk-wm831x.o
@@@@@@ -94,7 -93,7 -94,7 -95,6 -93,7 +97,6 @@@@@@ obj-y                                 += imx
     obj-y                                      += ingenic/
     obj-$(CONFIG_ARCH_K3)                      += keystone/
     obj-$(CONFIG_ARCH_KEYSTONE)                += keystone/
--- -obj-$(CONFIG_MACH_LOONGSON32)              += loongson1/
     obj-y                                      += mediatek/
     obj-$(CONFIG_ARCH_MESON)           += meson/
     obj-y                                      += microchip/

diff --combined drivers/clk/mediatek/clk-pllfh.c
index f135b32c6dbedc69eebb5d6516dd9fd41499b914,7b6e051443f4887f205d44b06933656f9b7a49f4,f48780bec5077ae27aad22bd59a654e94734bdcb,f48780bec5077ae27aad22bd59a654e94734bdcb,f48780bec5077ae27aad22bd59a654e94734bdcb..3a2b3f90be25d5925a19890c82823784791dd70a
--- 1/drivers/clk/mediatek/clk-pllfh.c
--- 2/drivers/clk/mediatek/clk-pllfh.c
--- 3/drivers/clk/mediatek/clk-pllfh.c
--- 4/drivers/clk/mediatek/clk-pllfh.c
--- 5/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@@@@@ -75,13 -75,13 -75,13 -75,13 -75,13 +75,13 @@@@@@ void fhctl_parse_dt(const u8 *compatibl
        base = of_iomap(node, 0);
        if (!base) {
                pr_err("%s(): ioremap failed\n", __func__);
 ----           return;
 ++++           goto out_node_put;
        }
     
        num_clocks = of_clk_get_parent_count(node);
        if (!num_clocks) {
                pr_err("%s(): failed to get clocks property\n", __func__);
 ----           return;
 ++++           goto err;
        }
     
        for (i = 0; i < num_clocks; i++) {
@@@@@@ -102,23 -102,19 -102,16 -102,16 -102,16 +102,26 @@@@@@
                pllfh->state.ssc_rate = ssc_rate;
                pllfh->state.base = base;
        }
 ++++
 ++++out_node_put:
 ++++   of_node_put(node);
 ++++   return;
 ++++err:
 ++++   iounmap(base);
 ++++   goto out_node_put;
     }
+ +++EXPORT_SYMBOL_GPL(fhctl_parse_dt);
     
- ---static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
+ +++static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
     {
        struct fh_pll_regs *regs = &fh->regs;
        const struct fhctl_offset *offset;
        void __iomem *base = pllfh_data->state.base;
        void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
     
- ---   offset = fhctl_get_offset_table();
+ +++   offset = fhctl_get_offset_table(pllfh_data->data.fh_ver);
+ +++   if (IS_ERR(offset))
+ +++           return PTR_ERR(offset);
     
        regs->reg_hp_en = base + offset->offset_hp_en;
        regs->reg_clk_con = base + offset->offset_clk_con;
@@@@@@ -136,6 -132,8 -129,6 -129,6 -129,6 +139,8 @@@@@@
        fh->lock = &pllfh_lock;
     
        fh->ops = fhctl_get_ops();
+ +++
+ +++   return 0;
     }
     
     static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
@@@@@@ -149,20 -147,29 -142,20 -142,20 -142,20 +154,29 @@@@@@ mtk_clk_register_pllfh(const struct mtk
     {
        struct clk_hw *hw;
        struct mtk_fh *fh;
+ +++   int ret;
     
        fh = kzalloc(sizeof(*fh), GFP_KERNEL);
        if (!fh)
                return ERR_PTR(-ENOMEM);
     
- ---   pllfh_init(fh, pllfh_data);
+ +++   ret = pllfh_init(fh, pllfh_data);
+ +++   if (ret) {
+ +++           hw = ERR_PTR(ret);
+ +++           goto out;
+ +++   }
     
        hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
                                      &mtk_pllfh_ops);
     
+ +++   if (IS_ERR(hw))
+ +++           goto out;
+ +++
+ +++   fhctl_hw_init(fh);
+ +++
+ +++out:
        if (IS_ERR(hw))
                kfree(fh);
- ---   else
- ---           fhctl_hw_init(fh);
     
        return hw;
     }
@@@@@@ -241,6 -248,7 -234,6 -234,6 -234,6 +255,7 @@@@@@ err
     
        return PTR_ERR(hw);
     }
+ +++EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs);
     
     void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
                               struct mtk_pllfh_data *pllfhs, int num_fhs,
@@@@@@ -280,3 -288,4 -273,3 -273,3 -273,3 +295,4 @@@@@@
     
        iounmap(base);
     }
+ +++EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs);