watchdog: bindings: Provide ST bindings for ST's LPC Watchdog device
authorLee Jones <lee.jones@linaro.org>
Thu, 9 Apr 2015 14:47:30 +0000 (15:47 +0100)
committerWim Van Sebroeck <wim@iguana.be>
Mon, 22 Jun 2015 13:53:50 +0000 (15:53 +0200)
On current ST platforms the LPC controls a number of functions including
Watchdog and Real Time Clock.  This patch provides the bindings used to
configure LPC in Watchdog mode.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt b/Documentation/devicetree/bindings/watchdog/st_lpc_wdt.txt
new file mode 100644 (file)
index 0000000..388c88a
--- /dev/null
@@ -0,0 +1,38 @@
+STMicroelectronics Low Power Controller (LPC) - Watchdog
+========================================================
+
+LPC currently supports Watchdog OR Real Time Clock functionality.
+
+[See: ../rtc/rtc-st-lpc.txt for RTC options]
+
+Required properties
+
+- compatible   : Must be one of: "st,stih407-lpc" "st,stih416-lpc"
+                                 "st,stih415-lpc" "st,stid127-lpc"
+- reg          : LPC registers base address + size
+- interrupts    : LPC interrupt line number and associated flags
+- clocks       : Clock used by LPC device (See: ../clock/clock-bindings.txt)
+- st,lpc-mode  : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or
+                 ST_LPC_MODE_WDT [1].  One (and only one) mode must be
+                 selected.
+
+Required properties [watchdog mode]
+
+- st,syscfg    : Phandle to syscfg node used to enable watchdog and configure
+                 CPU reset type.
+- timeout-sec  : Watchdog timeout in seconds
+
+Optional properties [watchdog mode]
+
+- st,warm-reset        : If present reset type will be 'warm' - if not it will be cold
+
+Example:
+       lpc@fde05000 {
+               compatible      = "st,stih407-lpc";
+               reg             = <0xfde05000 0x1000>;
+               clocks          = <&clk_s_d3_flexgen CLK_LPC_0>;
+               st,syscfg       = <&syscfg_core>;
+               timeout-sec     = <120>;
+               st,lpc-mode     = <ST_LPC_MODE_WDT>;
+               st,warm-reset;
+       };