drm/amdgpu: correct umc poison mode set value

For GFX 11.0.3, Due to security policy, there is no way to check UcFatalEn
field of UMCCH0_0_GeccCtrl to identify UMC poison mode. This is workaround
force set umc poison mode as 1 for GFX 11.0.3

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
index b7da4528cf0a48f759b7648e2739b87182894706..da394bc06bbaaf95837b048cc2146501940fa478 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
@@ -340,29 +340,13 @@ static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev)
        }
 }
 
-static uint32_t umc_v8_10_query_ras_poison_mode_per_channel(
-                                               struct amdgpu_device *adev,
-                                               uint32_t umc_reg_offset)
-{
-       uint32_t ecc_ctrl_addr, ecc_ctrl;
-
-       ecc_ctrl_addr =
-               SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccCtrl);
-       ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr +
-                                       umc_reg_offset) * 4);
-
-       return REG_GET_FIELD(ecc_ctrl, UMCCH0_0_GeccCtrl, UCFatalEn);
-}
-
 static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)
 {
-       uint32_t umc_reg_offset  = 0;
-
-       /* Enabling fatal error in umc node0 instance0 channel0 will be
-        * considered as fatal error mode
+       /*
+        * Force return true, because UMCCH0_0_GeccCtrl
+        * is not accessible from host side
         */
-       umc_reg_offset = get_umc_v8_10_reg_offset(adev, 0, 0, 0);
-       return !umc_v8_10_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
+       return true;
 }
 
 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {