x86/mce: Add Zhaoxin MCE support

All newer Zhaoxin CPUs are compatible with Intel's Machine-Check
Architecture, so add support for them.

 [ bp: Reflow comment in vendor_disable_error_reporting() and massage
   commit message. ]

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: CooperYan@zhaoxin.com
Cc: DavidWang@zhaoxin.com
Cc: HerryYang@zhaoxin.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: QiyuanWang@zhaoxin.com
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/1568787573-1297-2-git-send-email-TonyWWang-oc@zhaoxin.com

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 743370ee49835650750e331c63ca985b8474e33b..a780fe02aa47f98258e893f8d39251e675dff505 100644 (file)
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -488,8 +488,9 @@ int mce_usable_address(struct mce *m)
        if (!(m->status & MCI_STATUS_ADDRV))
                return 0;
 
-       /* Checks after this one are Intel-specific: */
-       if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+       /* Checks after this one are Intel/Zhaoxin-specific: */
+       if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
+           boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
                return 1;
 
        if (!(m->status & MCI_STATUS_MISCV))
@@ -507,10 +508,13 @@ EXPORT_SYMBOL_GPL(mce_usable_address);
 
 bool mce_is_memory_error(struct mce *m)
 {
-       if (m->cpuvendor == X86_VENDOR_AMD ||
-           m->cpuvendor == X86_VENDOR_HYGON) {
+       switch (m->cpuvendor) {
+       case X86_VENDOR_AMD:
+       case X86_VENDOR_HYGON:
                return amd_mce_is_memory_error(m);
-       } else if (m->cpuvendor == X86_VENDOR_INTEL) {
+
+       case X86_VENDOR_INTEL:
+       case X86_VENDOR_ZHAOXIN:
                /*
                 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
                 *
@@ -527,9 +531,10 @@ bool mce_is_memory_error(struct mce *m)
                return (m->status & 0xef80) == BIT(7) ||
                       (m->status & 0xef00) == BIT(8) ||
                       (m->status & 0xeffc) == 0xc;
-       }
 
-       return false;
+       default:
+               return false;
+       }
 }
 EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
@@ -1697,6 +1702,18 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                if (c->x86 == 6 && c->x86_model == 45)
                        quirk_no_way_out = quirk_sandybridge_ifu;
        }
+
+       if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+               /*
+                * All newer Zhaoxin CPUs support MCE broadcasting. Enable
+                * synchronization with a one second timeout.
+                */
+               if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+                       if (cfg->monarch_timeout < 0)
+                               cfg->monarch_timeout = USEC_PER_SEC;
+               }
+       }
+
        if (cfg->monarch_timeout < 0)
                cfg->monarch_timeout = 0;
        if (cfg->bootlog != 0)
@@ -2014,15 +2031,16 @@ static void mce_disable_error_reporting(void)
 static void vendor_disable_error_reporting(void)
 {
        /*
-        * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs
-        * are socket-wide.
-        * Disabling them for just a single offlined CPU is bad, since it will
-        * inhibit reporting for all shared resources on the socket like the
-        * last level cache (LLC), the integrated memory controller (iMC), etc.
+        * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
+        * MSRs are socket-wide. Disabling them for just a single offlined CPU
+        * is bad, since it will inhibit reporting for all shared resources on
+        * the socket like the last level cache (LLC), the integrated memory
+        * controller (iMC), etc.
         */
        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
            boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
-           boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+           boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+           boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
                return;
 
        mce_disable_error_reporting();