drm/amdgpu: improve wait logic at fence polling

Accomplish this by reading the seq number right away instead of sleep
for 5us. There are certain cases where the fence is ready almost
immediately. Sleep number granularity was also reduced as the majority
of the kiq tlb flush takes between 2us to 6us.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 1994eafd3e71a21f1ef73ca6e87fb6a289d61c11..b7d648dd0170bb5640856c1d6a94fb0ac72e5e95 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -376,14 +376,11 @@ signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
                                      uint32_t wait_seq,
                                      signed long timeout)
 {
-       uint32_t seq;
-
-       do {
-               seq = amdgpu_fence_read(ring);
-               udelay(5);
-               timeout -= 5;
-       } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 
+       while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout > 0) {
+               udelay(2);
+               timeout -= 2;
+       }
        return timeout > 0 ? timeout : 0;
 }
 /**