net: stmmac: use common LPI_CTRL_STATUS bit definitions
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Wed, 5 Feb 2025 13:40:31 +0000 (13:40 +0000)
committerJakub Kicinski <kuba@kernel.org>
Fri, 7 Feb 2025 19:56:10 +0000 (11:56 -0800)
The bit definitions for the LPI control/status register are
identical across all MAC versions, with the exception that some
bits may not be implemented. Provide definitions for bits in this
register in common.h, convert to use them, and remove the core-
specific definitions.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1tffdn-003ZIN-9p@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

index e25db747a81a5bf2c5b11298b3be1ddebfae4f32..55053528e49841ed4f581a1bd7d6854f0ccafd71 100644 (file)
@@ -530,6 +530,20 @@ struct dma_features {
 #define STMMAC_DEFAULT_TWT_LS  0x1E
 #define STMMAC_ET_MAX          0xFFFFF
 
+/* Common LPI register bits */
+#define LPI_CTRL_STATUS_LPITCSE        BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */
+#define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */
+#define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
+#define LPI_CTRL_STATUS_PLSEN  BIT(18) /* Enable PHY Link Status */
+#define LPI_CTRL_STATUS_PLS    BIT(17) /* PHY Link Status */
+#define LPI_CTRL_STATUS_LPIEN  BIT(16) /* LPI Enable */
+#define LPI_CTRL_STATUS_RLPIST BIT(9)  /* Receive LPI state, gmac1000 only? */
+#define LPI_CTRL_STATUS_TLPIST BIT(8)  /* Transmit LPI state, gmac1000 only? */
+#define LPI_CTRL_STATUS_RLPIEX BIT(3)  /* Receive LPI Exit */
+#define LPI_CTRL_STATUS_RLPIEN BIT(2)  /* Receive LPI Entry */
+#define LPI_CTRL_STATUS_TLPIEX BIT(1)  /* Transmit LPI Exit */
+#define LPI_CTRL_STATUS_TLPIEN BIT(0)  /* Transmit LPI Entry */
+
 #define STMMAC_CHAIN_MODE      0x1
 #define STMMAC_RING_MODE       0x2
 
index 600fea8f712fd65bbb0c60a6f4464be6a5c04c3c..967a16212faf008bc7b5e43031e2d85800c5c467 100644 (file)
@@ -59,22 +59,11 @@ enum power_event {
 /* Energy Efficient Ethernet (EEE)
  *
  * LPI status, timer and control register offset
+ * For LPI control and status bit definitions, see common.h.
  */
 #define LPI_CTRL_STATUS        0x0030
 #define LPI_TIMER_CTRL 0x0034
 
-/* LPI control and status defines */
-#define LPI_CTRL_STATUS_LPITXA 0x00080000      /* Enable LPI TX Automate */
-#define LPI_CTRL_STATUS_PLSEN  0x00040000      /* Enable PHY Link Status */
-#define LPI_CTRL_STATUS_PLS    0x00020000      /* PHY Link Status */
-#define LPI_CTRL_STATUS_LPIEN  0x00010000      /* LPI Enable */
-#define LPI_CTRL_STATUS_RLPIST 0x00000200      /* Receive LPI state */
-#define LPI_CTRL_STATUS_TLPIST 0x00000100      /* Transmit LPI state */
-#define LPI_CTRL_STATUS_RLPIEX 0x00000008      /* Receive LPI Exit */
-#define LPI_CTRL_STATUS_RLPIEN 0x00000004      /* Receive LPI Entry */
-#define LPI_CTRL_STATUS_TLPIEX 0x00000002      /* Transmit LPI Exit */
-#define LPI_CTRL_STATUS_TLPIEN 0x00000001      /* Transmit LPI Entry */
-
 /* GMAC HW ADDR regs */
 #define GMAC_ADDR_HIGH(reg)    ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
                                 0x00000040 + (reg * 8))
index 184d41a306af08e9b6a72501240e644ee9d65449..42fe29a4e300b31cc5c394140c6146e4a3c8ed7b 100644 (file)
@@ -177,23 +177,13 @@ enum power_event {
 /* Energy Efficient Ethernet (EEE) for GMAC4
  *
  * LPI status, timer and control register offset
+ * For LPI control and status bit definitions, see common.h.
  */
 #define GMAC4_LPI_CTRL_STATUS  0xd0
 #define GMAC4_LPI_TIMER_CTRL   0xd4
 #define GMAC4_LPI_ENTRY_TIMER  0xd8
 #define GMAC4_MAC_ONEUS_TIC_COUNTER    0xdc
 
-/* LPI control and status defines */
-#define GMAC4_LPI_CTRL_STATUS_LPITCSE  BIT(21) /* LPI Tx Clock Stop Enable */
-#define GMAC4_LPI_CTRL_STATUS_LPIATE   BIT(20) /* LPI Timer Enable */
-#define GMAC4_LPI_CTRL_STATUS_LPITXA   BIT(19) /* Enable LPI TX Automate */
-#define GMAC4_LPI_CTRL_STATUS_PLS      BIT(17) /* PHY Link Status */
-#define GMAC4_LPI_CTRL_STATUS_LPIEN    BIT(16) /* LPI Enable */
-#define GMAC4_LPI_CTRL_STATUS_RLPIEX   BIT(3) /* Receive LPI Exit */
-#define GMAC4_LPI_CTRL_STATUS_RLPIEN   BIT(2) /* Receive LPI Entry */
-#define GMAC4_LPI_CTRL_STATUS_TLPIEX   BIT(1) /* Transmit LPI Exit */
-#define GMAC4_LPI_CTRL_STATUS_TLPIEN   BIT(0) /* Transmit LPI Entry */
-
 /* MAC Debug bitmap */
 #define GMAC_DEBUG_TFCSTS_MASK         GENMASK(18, 17)
 #define GMAC_DEBUG_TFCSTS_SHIFT                17
index 17bf836eba7fa76c9f51bf6768fee14aa0eef3b2..c324aaf691e0d18df6401ef24a631d8a2bc680ff 100644 (file)
@@ -387,11 +387,11 @@ static void dwmac4_set_eee_mode(struct mac_device_info *hw,
         * state.
         */
        value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
-       value &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
-       value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
+       value &= ~LPI_CTRL_STATUS_LPIATE;
+       value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 
        if (en_tx_lpi_clockgating)
-               value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
+               value |= LPI_CTRL_STATUS_LPITCSE;
 
        writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 }
@@ -402,8 +402,8 @@ static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
        u32 value;
 
        value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
-       value &= ~(GMAC4_LPI_CTRL_STATUS_LPIATE | GMAC4_LPI_CTRL_STATUS_LPIEN |
-                  GMAC4_LPI_CTRL_STATUS_LPITXA);
+       value &= ~(LPI_CTRL_STATUS_LPIATE | LPI_CTRL_STATUS_LPIEN |
+                  LPI_CTRL_STATUS_LPITXA);
        writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 }
 
@@ -415,9 +415,9 @@ static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
        value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 
        if (link)
-               value |= GMAC4_LPI_CTRL_STATUS_PLS;
+               value |= LPI_CTRL_STATUS_PLS;
        else
-               value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
+               value &= ~LPI_CTRL_STATUS_PLS;
 
        writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 }
@@ -433,12 +433,12 @@ static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, u32 et)
 
        /* Enable/disable LPI entry timer */
        regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
-       regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
+       regval |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 
        if (et)
-               regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
+               regval |= LPI_CTRL_STATUS_LPIATE;
        else
-               regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
+               regval &= ~LPI_CTRL_STATUS_LPIATE;
 
        writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
 }
@@ -851,17 +851,17 @@ static int dwmac4_irq_status(struct mac_device_info *hw,
                /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
                u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 
-               if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
+               if (status & LPI_CTRL_STATUS_TLPIEN) {
                        ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
                        x->irq_tx_path_in_lpi_mode_n++;
                }
-               if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
+               if (status & LPI_CTRL_STATUS_TLPIEX) {
                        ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
                        x->irq_tx_path_exit_lpi_mode_n++;
                }
-               if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
+               if (status & LPI_CTRL_STATUS_RLPIEN)
                        x->irq_rx_path_in_lpi_mode_n++;
-               if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
+               if (status & LPI_CTRL_STATUS_RLPIEX)
                        x->irq_rx_path_exit_lpi_mode_n++;
        }
 
index 20027d3c25a79a6cc6af91c857a99dfc6ce35531..a03f5d77156635ac2b448559c7ded18944b163bb 100644 (file)
 #define XGMAC_MGKPKTEN                 BIT(1)
 #define XGMAC_PWRDWN                   BIT(0)
 #define XGMAC_LPI_CTRL                 0x000000d0
-#define XGMAC_TXCGE                    BIT(21)
-#define XGMAC_LPITXA                   BIT(19)
-#define XGMAC_PLS                      BIT(17)
-#define XGMAC_LPITXEN                  BIT(16)
-#define XGMAC_RLPIEX                   BIT(3)
-#define XGMAC_RLPIEN                   BIT(2)
-#define XGMAC_TLPIEX                   BIT(1)
-#define XGMAC_TLPIEN                   BIT(0)
+/* For definitions, see LPI_CTRL_STATUS_xxx in common.h */
 #define XGMAC_LPI_TIMER_CTRL           0x000000d4
 #define XGMAC_HW_FEATURE0              0x0000011c
 #define XGMAC_HWFEAT_EDMA              BIT(31)
index 9a60a6e8f6331ed413e6af5e64041c2a5ea9264d..19cfb1dcb3324b7f9dba59657ea13b22edd0bfd9 100644 (file)
@@ -316,17 +316,17 @@ static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
        if (stat & XGMAC_LPIIS) {
                u32 lpi = readl(ioaddr + XGMAC_LPI_CTRL);
 
-               if (lpi & XGMAC_TLPIEN) {
+               if (lpi & LPI_CTRL_STATUS_TLPIEN) {
                        ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
                        x->irq_tx_path_in_lpi_mode_n++;
                }
-               if (lpi & XGMAC_TLPIEX) {
+               if (lpi & LPI_CTRL_STATUS_TLPIEX) {
                        ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
                        x->irq_tx_path_exit_lpi_mode_n++;
                }
-               if (lpi & XGMAC_RLPIEN)
+               if (lpi & LPI_CTRL_STATUS_RLPIEN)
                        x->irq_rx_path_in_lpi_mode_n++;
-               if (lpi & XGMAC_RLPIEX)
+               if (lpi & LPI_CTRL_STATUS_RLPIEX)
                        x->irq_rx_path_exit_lpi_mode_n++;
        }
 
@@ -433,9 +433,9 @@ static void dwxgmac2_set_eee_mode(struct mac_device_info *hw,
 
        value = readl(ioaddr + XGMAC_LPI_CTRL);
 
-       value |= XGMAC_LPITXEN | XGMAC_LPITXA;
+       value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
        if (en_tx_lpi_clockgating)
-               value |= XGMAC_TXCGE;
+               value |= LPI_CTRL_STATUS_LPITCSE;
 
        writel(value, ioaddr + XGMAC_LPI_CTRL);
 }
@@ -446,7 +446,7 @@ static void dwxgmac2_reset_eee_mode(struct mac_device_info *hw)
        u32 value;
 
        value = readl(ioaddr + XGMAC_LPI_CTRL);
-       value &= ~(XGMAC_LPITXEN | XGMAC_LPITXA | XGMAC_TXCGE);
+       value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA | LPI_CTRL_STATUS_LPITCSE);
        writel(value, ioaddr + XGMAC_LPI_CTRL);
 }
 
@@ -457,9 +457,9 @@ static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)
 
        value = readl(ioaddr + XGMAC_LPI_CTRL);
        if (link)
-               value |= XGMAC_PLS;
+               value |= LPI_CTRL_STATUS_PLS;
        else
-               value &= ~XGMAC_PLS;
+               value &= ~LPI_CTRL_STATUS_PLS;
        writel(value, ioaddr + XGMAC_LPI_CTRL);
 }