drm/nouveau/mc: s/intr_mask/intr_stat/
authorBen Skeggs <bskeggs@redhat.com>
Sun, 29 May 2016 22:27:22 +0000 (08:27 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 14 Jul 2016 01:53:25 +0000 (11:53 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
13 files changed:
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h

index e887df08e8cff08cbebbef03f1753a4bc1c0378c..6f10638ab9e436435d06cff2000188c5e1aa1835 100644 (file)
@@ -51,9 +51,9 @@ nvkm_mc_intr_rearm(struct nvkm_device *device)
 }
 
 static u32
-nvkm_mc_intr_mask(struct nvkm_mc *mc)
+nvkm_mc_intr_stat(struct nvkm_mc *mc)
 {
-       u32 intr = mc->func->intr_mask(mc);
+       u32 intr = mc->func->intr_stat(mc);
        if (WARN_ON_ONCE(intr == 0xffffffff))
                intr = 0; /* likely fallen off the bus */
        return intr;
@@ -71,7 +71,7 @@ nvkm_mc_intr(struct nvkm_device *device, bool *handled)
        if (unlikely(!mc))
                return;
 
-       intr = nvkm_mc_intr_mask(mc);
+       intr = nvkm_mc_intr_stat(mc);
        stat = nvkm_top_intr(device, intr, &subdevs);
        while (subdevs) {
                enum nvkm_devidx subidx = __ffs64(subdevs);
index 5c85b47f071d3a81645a5e3a24cfed5dd667947f..c3d66ef5dc129877607cbbbce62f02b39054cbf7 100644 (file)
@@ -57,7 +57,7 @@ g84_mc = {
        .intr = g84_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = g84_mc_reset,
 };
 
index 0280b43cc10c9eb2dfacbe31aee636488443fca1..93ad4982ce5f656544ffdf3ca16f886a32a8f8c2 100644 (file)
@@ -57,7 +57,7 @@ g98_mc = {
        .intr = g98_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = g98_mc_reset,
 };
 
index 8397e223bd4305295cf714463b099f5c63a8b5ac..b1126a5a8b047f18546dfbeebb55a08250c37fe6 100644 (file)
@@ -76,7 +76,7 @@ gf100_mc_intr_rearm(struct nvkm_mc *mc)
 }
 
 u32
-gf100_mc_intr_mask(struct nvkm_mc *mc)
+gf100_mc_intr_stat(struct nvkm_mc *mc)
 {
        struct nvkm_device *device = mc->subdev.device;
        u32 intr0 = nvkm_rd32(device, 0x000100);
@@ -96,7 +96,7 @@ gf100_mc = {
        .intr = gf100_mc_intr,
        .intr_unarm = gf100_mc_intr_unarm,
        .intr_rearm = gf100_mc_intr_rearm,
-       .intr_mask = gf100_mc_intr_mask,
+       .intr_stat = gf100_mc_intr_stat,
        .reset = gf100_mc_reset,
        .unk260 = gf100_mc_unk260,
 };
index 317464212c7d1eb75b28cf54dbb210912d2c9566..99426814c7f714ed4f211895356fc779d0dbd437 100644 (file)
@@ -52,7 +52,7 @@ gk104_mc = {
        .intr = gk104_mc_intr,
        .intr_unarm = gf100_mc_intr_unarm,
        .intr_rearm = gf100_mc_intr_rearm,
-       .intr_mask = gf100_mc_intr_mask,
+       .intr_stat = gf100_mc_intr_stat,
        .reset = gk104_mc_reset,
        .unk260 = gf100_mc_unk260,
 };
index 60b044f517ed5d70aec8d8f424322edf4afd821a..985f8cbab5c4368b5c6a0947b5d9872f3ad0a0a3 100644 (file)
@@ -29,7 +29,7 @@ gk20a_mc = {
        .intr = gk104_mc_intr,
        .intr_unarm = gf100_mc_intr_unarm,
        .intr_rearm = gf100_mc_intr_rearm,
-       .intr_mask = gf100_mc_intr_mask,
+       .intr_stat = gf100_mc_intr_stat,
        .reset = gk104_mc_reset,
 };
 
index aad0ba95bf180118ea9c5430cd9be6abb9dde93d..60c349a9d1f6e49e117d52a93d2a3dc5a25f466f 100644 (file)
@@ -59,7 +59,7 @@ gt215_mc = {
        .intr = gt215_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = gt215_mc_reset,
 };
 
index a062624e906b3396f4b5b74c3da704be4b1a9765..6509defd14609c1a9675424da7f45f3c6cf5ee8b 100644 (file)
@@ -56,7 +56,7 @@ nv04_mc_intr_rearm(struct nvkm_mc *mc)
 }
 
 u32
-nv04_mc_intr_mask(struct nvkm_mc *mc)
+nv04_mc_intr_stat(struct nvkm_mc *mc)
 {
        return nvkm_rd32(mc->subdev.device, 0x000100);
 }
@@ -75,7 +75,7 @@ nv04_mc = {
        .intr = nv04_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = nv04_mc_reset,
 };
 
index 55f0b9166b52cb207dc5973076b584630d8674b6..9213107901e6de32f51973f2d6d086e2eb6f2edc 100644 (file)
@@ -39,7 +39,7 @@ nv11_mc = {
        .intr = nv11_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = nv04_mc_reset,
 };
 
index c40fa67f79a51d3d122a77011824ad34e591e3f0..64bf5bbf8146cb80e6ace6f69bdca9da0e9c0d2a 100644 (file)
@@ -48,7 +48,7 @@ nv17_mc = {
        .intr = nv17_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = nv17_mc_reset,
 };
 
index cc56271db5643695add777bad34059c27d7f9b49..65fa44a64b985f12437fa3fa7473eaa704b98927 100644 (file)
@@ -43,7 +43,7 @@ nv44_mc = {
        .intr = nv17_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = nv17_mc_reset,
 };
 
index 343b6078580de8bee982c56c267db9d48a6858a0..fe93b4fd71002ccbfcab3505c0a6b13f4bf039c1 100644 (file)
@@ -50,7 +50,7 @@ nv50_mc = {
        .intr = nv50_mc_intr,
        .intr_unarm = nv04_mc_intr_unarm,
        .intr_rearm = nv04_mc_intr_rearm,
-       .intr_mask = nv04_mc_intr_mask,
+       .intr_stat = nv04_mc_intr_stat,
        .reset = nv17_mc_reset,
 };
 
index bace7fc3c232681bdcfb3b6414e1e94f5aa1c4e9..0229c7e0172928a76e4f9360a8e4b974da7a6496 100644 (file)
@@ -22,7 +22,7 @@ struct nvkm_mc_func {
        /* enable reporting of interrupts to host */
        void (*intr_rearm)(struct nvkm_mc *);
        /* retrieve pending interrupt mask (NV_PMC_INTR) */
-       u32 (*intr_mask)(struct nvkm_mc *);
+       u32 (*intr_stat)(struct nvkm_mc *);
        const struct nvkm_mc_map *reset;
        void (*unk260)(struct nvkm_mc *, u32);
 };
@@ -30,7 +30,7 @@ struct nvkm_mc_func {
 void nv04_mc_init(struct nvkm_mc *);
 void nv04_mc_intr_unarm(struct nvkm_mc *);
 void nv04_mc_intr_rearm(struct nvkm_mc *);
-u32 nv04_mc_intr_mask(struct nvkm_mc *);
+u32 nv04_mc_intr_stat(struct nvkm_mc *);
 extern const struct nvkm_mc_map nv04_mc_reset[];
 
 extern const struct nvkm_mc_map nv17_mc_intr[];
@@ -42,7 +42,7 @@ void nv50_mc_init(struct nvkm_mc *);
 
 void gf100_mc_intr_unarm(struct nvkm_mc *);
 void gf100_mc_intr_rearm(struct nvkm_mc *);
-u32 gf100_mc_intr_mask(struct nvkm_mc *);
+u32 gf100_mc_intr_stat(struct nvkm_mc *);
 void gf100_mc_unk260(struct nvkm_mc *, u32);
 
 extern const struct nvkm_mc_map gk104_mc_intr[];