drm/amd/display: Resolve Coverity Issues

[WHY]
Remove coverity issues that were originally ignored.

[HOW]
Ran coverity locally on driver, used output report to find existing
coverity issues, resolved them

Reviewed-by: Nicholas Choi <nicholas.choi@amd.com>
Signed-off-by: Daniel Sa <Daniel.Sa@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
index 1c773bbb999294f2578849954066ec86565f49b1..eeb96c45565841e1e1069cb92757eb32b76fd8b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
@@ -5,7 +5,6 @@
 #ifndef __DML_TOP_TYPES_H__
 #define __DML_TOP_TYPES_H__
 
-#include "dml_top_types.h"
 #include "dml_top_display_cfg_types.h"
 #include "dml_top_soc_parameter_types.h"
 #include "dml_top_policy_types.h"

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index ca4f23d105fc282eb015dbef6b37126818f49caa..3ea54fd52e4683167d3c49038c3fab351e961bed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -2085,7 +2085,11 @@ static void CalculateDCCConfiguration(
        unsigned int full_swath_bytes_vert_wc_l;
        unsigned int full_swath_bytes_vert_wc_c;
 
-       yuv420 = dml_is_420(SourcePixelFormat);
+       if (dml_is_420(SourcePixelFormat))
+               yuv420 = 1;
+       else
+               yuv420 = 0;
+
        horz_div_l = 1;
        horz_div_c = 1;
        vert_div_l = 1;
@@ -2553,8 +2557,11 @@ static void calculate_mcache_setting(
                l->luma_time_factor = (double)l->mvmpg_width_c / l->mvmpg_width_l * 2;
 
        // The algorithm starts with computing a non-integer, avg_mcache_element_size_l/c:
-       l->avg_mcache_element_size_l = l->meta_row_width_l / *p->num_mcaches_l;
-       if (l->is_dual_plane) {
+       if (*p->num_mcaches_l) {
+               l->avg_mcache_element_size_l = l->meta_row_width_l / *p->num_mcaches_l;
+       }
+
+       if (l->is_dual_plane && *p->num_mcaches_c) {
                l->avg_mcache_element_size_c = l->meta_row_width_c / *p->num_mcaches_c;
 
                if (!p->imall_enable || (*p->mall_comb_mcache_l == *p->mall_comb_mcache_c)) {
@@ -2683,9 +2690,9 @@ static double dml_get_return_bandwidth_available(
        double ideal_fabric_bandwidth = fclk_mhz * (double)soc->fabric_datapath_to_dcn_data_return_bytes;
        double ideal_dram_bandwidth = dram_bw_mbps; //dram_speed_mts * soc->clk_table.dram_config.channel_count * soc->clk_table.dram_config.channel_width_bytes;
 
-       double derate_sdp_factor = 1;
-       double derate_fabric_factor = 1;
-       double derate_dram_factor = 1;
+       double derate_sdp_factor;
+       double derate_fabric_factor;
+       double derate_dram_factor;
 
        double derate_sdp_bandwidth;
        double derate_fabric_bandwidth;
@@ -7209,7 +7216,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
        mode_lib->ms.support.WritebackLatencySupport = true;
        for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
                if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.enable == true &&
-                       (mode_lib->ms.WriteBandwidth[k] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / mode_lib->soc.qos_parameters.writeback.base_latency_us)) {
+                       (mode_lib->ms.WriteBandwidth[k] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib->soc.qos_parameters.writeback.base_latency_us))) {
                        mode_lib->ms.support.WritebackLatencySupport = false;
                }
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
index 8e68a8094658fedad1f42c2946685eb0ead5fcf0..a31db5742675d001cbce130af583f73673ecf482 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
@@ -497,7 +497,6 @@ bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in
                                                        in_out->cfg_support_info->plane_support_info[i].dpps_used)) {
                                                        result = false;
                                                } else {
-                                                       free_pipes -= planes_on_stream;
                                                        break;
                                                }
                                        } else {
@@ -666,7 +665,7 @@ bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_su
        struct dml2_pmo_instance *pmo = in_out->instance;
        unsigned int stream_index;
        bool success = false;
-       bool reached_end = true;
+       bool reached_end;
 
        memcpy(in_out->optimized_display_config, in_out->base_display_config, sizeof(struct display_configuation_with_meta));
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 30767f330fd4869a9122f971dfeb8fb92e28d7ce..3bb5eb2e79aecb3f94df41e0debc3cb01c07a5df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -334,7 +334,6 @@ bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_o
                                                        in_out->cfg_support_info->plane_support_info[i].dpps_used)) {
                                                        result = false;
                                                } else {
-                                                       free_pipes -= planes_on_stream;
                                                        break;
                                                }
                                        } else {
@@ -672,8 +671,6 @@ bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out)
                        /* populate list */
                        expand_base_strategies(pmo, base_strategy_list_4_display, base_strategy_list_4_display_size, 4);
                        break;
-               default:
-                       break;
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c
index dc8af4dd04108219fc5badb71c70adbb88ab1768..d0e026d981b503eada1e74f6de3fc43f5d7529fa 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c
@@ -219,7 +219,6 @@ bool dml2_top_optimization_perform_optimization_phase_1(struct dml2_optimization
        copy_display_configuration_with_meta(&l->cur_candidate_display_cfg, params->display_config);
        highest_state = l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency;
        lowest_state = 0;
-       cur_state = 0;
 
        while (highest_state > lowest_state) {
                cur_state = (highest_state + lowest_state) / 2;