drm/amdgpu: add gfx support for van gogh (v3)

Add van gogh checks to gfx10 code.

v2: squash in fixes
v3: fix mode

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9792ec737029aa1d57c96f8d9aadea580eec6b46..17c688a32f9eb212e69b53d9a25355ca4a398e35 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -152,6 +152,13 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3554,6 +3561,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
                break;
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfx.cp_fw_write_wait = true;
                break;
        default:
@@ -3655,6 +3663,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        case CHIP_NAVY_FLOUNDER:
                chip_name = "navy_flounder";
                break;
+       case CHIP_VANGOGH:
+               chip_name = "vangogh";
+               break;
        default:
                BUG();
        }
@@ -4189,6 +4200,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
                break;
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4312,6 +4324,7 @@ static int gfx_v10_0_sw_init(void *handle)
                break;
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
@@ -4567,7 +4580,8 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
        /* for ASICs that integrates GFX v10.3
         * pa_sc_tile_steering_override should be set to 0 */
        if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-           adev->asic_type == CHIP_NAVY_FLOUNDER)
+           adev->asic_type == CHIP_NAVY_FLOUNDER ||
+           adev->asic_type == CHIP_VANGOGH)
                return 0;
 
        /* init num_sc */
@@ -5804,6 +5818,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
                                    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
                WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5937,6 +5952,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                switch (adev->asic_type) {
                case CHIP_SIENNA_CICHLID:
                case CHIP_NAVY_FLOUNDER:
+               case CHIP_VANGOGH:
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
                        break;
                default:
@@ -5947,6 +5963,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
                switch (adev->asic_type) {
                case CHIP_SIENNA_CICHLID:
                case CHIP_NAVY_FLOUNDER:
+               case CHIP_VANGOGH:
                        WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
                                     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
                                      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6041,6 +6058,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
                tmp &= 0xffffff00;
                tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6761,6 +6779,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
                        return false;
                }
                break;
+       case CHIP_VANGOGH:
+               return true;
        default:
                data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
                WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
@@ -6788,6 +6808,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
                data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
                        GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7082,6 +7103,7 @@ static int gfx_v10_0_soft_reset(void *handle)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
                        grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
                                                        GRBM_SOFT_RESET,
@@ -7181,6 +7203,7 @@ static int gfx_v10_0_early_init(void *handle)
                break;
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
                break;
        default:
@@ -7234,6 +7257,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
                /* wait for RLC_SAFE_MODE */
@@ -7266,6 +7290,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
                break;
        default:
@@ -7577,6 +7602,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                gfx_v10_0_update_gfx_clock_gating(adev,
                                                 state == AMD_CG_STATE_GATE);
                break;
@@ -8679,6 +8705,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
        case CHIP_NAVI14:
        case CHIP_SIENNA_CICHLID:
        case CHIP_NAVY_FLOUNDER:
+       case CHIP_VANGOGH:
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                break;
        case CHIP_NAVI12: