drm/amd/display: Move define from internal header to dmub_cmd.h
authorYongqiang Sun <yongqiang.sun@amd.com>
Mon, 22 Feb 2021 17:30:18 +0000 (12:30 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 24 Mar 2021 03:02:27 +0000 (23:02 -0400)
[Why & How]
Fix linux compile error

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

index 99356d0a048b38f592667e4cda67149bd1930191..a9635b5abe55f2bdde62026911cb97d4caa5249c 100644 (file)
@@ -172,6 +172,18 @@ union dmub_fw_meta {
 
 #pragma pack(pop)
 
+//==============================================================================
+//< DMUB Trace Buffer>================================================================
+//==============================================================================
+typedef uint32_t dmub_trace_code_t;
+
+struct dmcub_trace_buf_entry {
+       dmub_trace_code_t trace_code;
+       uint32_t tick_count;
+       uint32_t param0;
+       uint32_t param1;
+};
+
 //==============================================================================
 //< DMUB_STATUS>================================================================
 //==============================================================================
index eb9bf4da088a48fad38739b95d9d2f51936c2879..55ee27defd0f15cf5c8f25a66100bd86a5c79791 100644 (file)
@@ -31,7 +31,6 @@
 #include "dmub_dcn301.h"
 #include "dmub_dcn302.h"
 #include "os_types.h"
-#include "dmub_trace_buffer.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
  * added below or above this line unless they reside within the DMUB
@@ -475,7 +474,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
                cw5.region.top = cw5.region.base + tracebuff_fb->size;
 
                outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
-               outbox0.top = outbox0.base + sizeof(struct dmcub_trace_buf_entry) * PERF_TRACE_MAX_ENTRY;
+               outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
 
 
                cw6.offset.quad_part = fw_state_fb->gpu_addr;
@@ -518,7 +517,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
        dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
        outbox0_rb_params.ctx = dmub;
        outbox0_rb_params.base_address = (void *)((uint64_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
-       outbox0_rb_params.capacity = sizeof(struct dmcub_trace_buf_entry) * PERF_TRACE_MAX_ENTRY;
+       outbox0_rb_params.capacity = tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
        dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
 
        if (dmub->hw_funcs.reset_release)